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NI 9683 User Guide and Specifications
Figure 18.
Connecting a Digital Device to a Sourcing DI Channel
The NI 9683 channel registers ON when the sinking-output is in the ON range. The channel
registers as OFF when the sinking-output is in the OFF range. If no device is connected to the
sourcing DI, the channel registers as OFF. Refer to the
information about the ON and OFF ranges of the sourcing DI.
Note
NI recommends that you leave sourcing DI channels that are not used in your
application unconnected to lower power dissipation through the onboard pull-up
resistor.
LVTTL Digital Input/Output
The NI 9683 provides connections for 32 LVTTL digital input/output channels.
The NI 9683 LVTTL DIO channels connect directly to the FPGA DIO on the
NI sbRIO-9605/9606 and are unbuffered and unprotected. Refer to the
more information about the maximum current.
Caution
Operating the LVTTL DIO outside the rated specifications may result in
permanent damage to the FPGA on NI sbRIO-9605/9606.
Figure 19.
Connecting to the LVTTL DIO Channels
If overshoot and undershoot aberrations and signal integrity are concerns for your application,
use a single load per line that does not exceed 25 pF. For edge sensitive signals, use channels
DIO0 through DIO15 for better signal integrity and crosstalk performance since these channels
have an individual GND pin.
The LVTTL DIO channels on the NI 9863 are routed with a 55
Ω
characteristic trace impedance.
Route all external circuitry with a similar impedance to ensure the best signal quality.
You should perform signal integrity measurements to test the effect of signal routing and cable
type on your application. To meet defined power-up states for outputs, use a pull-up or pull-down
resistor on the line.
NI 96
83
Extern
a
l
Power
Su
pply
+
–
S
inking-O
u
tp
u
t
Device
S
o
u
rcing DI
4.
3
2 k
Ω
VI P0/VI P1
GND
U
s
er
Bo
a
rd
NI
sb
RIO-9605/6
FPGA
DIO0
DIO
3
1
.
.
.
NI 96
83
Z
0
= 55
Ω
Z
0
= 55
Ω
Z
0
= 55
Ω
Z
0
= 55
Ω
