National Instruments NI 6584R, User Manual And Specifications

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NI 6584R User Guide and Specifications 12 ni.com
Your block diagram should now resemble the block diagram in Figure 7.
Figure 7. Data RW (Host).vi Block Diagram
20. Save the VI as
Data RW (Host).vi
.
Running the Host VI
1. Open the front panel of
Data RW (Host).vi
.
2. Click the Run button to run the VI.
3. Enter a number in the IO Module\TX control to push different values to all 16 channels. When you
use the half duplex version of the NI 6584R, the number you enter in the IO Module\TX appears
in the IO Module\RX control. When you use the full duplex version of the NI 6584R, the
IO Module\RX indicator returns the number 65,535 because all RX lines are floating.
4. Click the Stop button on the front panel and close the VI.
NI 6584 Component-Level Intellectual Property
The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP. NI FlexRIO
devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows users to insert HDL IP into an FPGA target, enabling VHDL code to
communicate directly with an FPGA VI.
• Socketed CLIP provides the same IP integration functionality of the user-defined CLIP, but also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module
socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external
adapter module connector interface.