National Instruments NI 651 Series, User Manual

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NI 651x User Manual
Figure 1-3.
NI 6512 Block Diagram
Figure 1-4. NI 6513 Block Diagram
Figure 1-5. NI 6514 Block Diagram
Ind us tri a l Digit a l
O u tp u t Control FPGA
O
u
tp
u
t Line
s
Progr a mm ab le
Power-Up S t a te s
W a tchdog Timer
64 Digit a l
O u tp u t s
PX.COM
PX.Vcc
PX.<0..7>
8
x8 B a nk I s ol a ted Digit a l O u tp u t Port s
PCI/PXI/Comp
a
ctPCI B
us
10 MHz
Clock
D a t a /Control
PCI B us
Interf a ce
D a t a /Control
Fl as h
Memory
Config u r a tion
Control
DO
x8 O u tp u t s per Port
Volt a ge
Reg u l a tor
I/O Connector
I/O Connector
PX.COM (Vcc)
PX.<0..7>
PX.GND
DO
x8 O u tp u t s per Port
x8 B a nk I s ol a ted Digit a l O u tp u t Port s
Ind us tri a l Digit a l
O u tp u t Control FPGA
O
u
tp
u
t Line
s
Progr a mm ab le
Power-Up S t a te s
W a tchdog Timer
PCI/PXI/Comp
a
ctPCI B
us
D a t a /Control
PCI B us
Interf a ce
D a t a /Control
Fl as h
Memory
Config u r a tion
Control
Volt a ge
Reg u l a tor
64 Digit a l
O u tp u t s
10 MHz
Clock
PX.Vcc
PX.<0..7>
PX.COM
8
x4 B a nk I s ol a ted Digit a l O u tp u t Port s
PCI/PXI/Comp
a
ctPCI B
us
D a t a /Control
PCI B us
Interf a ce
D a t a /Control
Fl as h
Memory
Config u r a tion
Control
10 MHz
Clock
3 2
Digit a l
O u tp u t s
Ind us tri a l Digit a l
I/O Control FPGA
DIO Line
s
Progr a mm ab le
Power-Up S t a te s
W a tchdog Timer
Ch a nge
Detection
Digit a l
Filtering
3 2
Digit a l
Inp u t s
I/O Connector
8
PX.COM
PX.<0..7>
Vcc
x4 B a nk I s ol a ted Digit a l Inp u t Port s
x8 Inp u t s per Port
DI
DO
x8 O u tp u t s per Port
Volt a ge
Reg u l a tor