NI 5731/5732/5733/5734R User Guide and Specifications
6
ni.com
Block Diagram
Figure 3 shows the NI 5731/5732/5733/5734 block diagram and signal flow to and from the
NI 5731/5732/5733/5734 component-level intellectual property (CLIP) by way of the adapter module
and the corresponding CLIP in LabVIEW FPGA.
Figure 3.
NI 5731/5732/5733/5734 Connector Signals and CLIP Signal Block Diagram
NI 5731/5732/5733/5734 Adapter Module
AI 0
AI 2
DIO Port 0 (0)
DIO Port 0 (1)
DIO Port 0 (2)
DIO Port 0 (3)
DIO Port 1 (0)
DIO Port 1 (1)
DIO Port 1 (2)
DIO Port 1 (3)
PFI 0
PFI 1
PFI 2
PFI 3
A
UX I/O
ADC
ADC Clock
ADC Data
Sample Clock
ADC
LabVIEW FPGA CLIP
ADC Clock
ADC Data
ADC
Interface
ADC
Interface
AI 0
AI 2
AI 0 Over Range
AI 2 Over Range
16
DC Over Voltage
4
SPI Device Select
SPI Read
SPI Write
SPI Write Data
SPI Address
SPI Idle
32
32
DIO Port 0 WE
DIO Port 0 Rd Data (0)
DIO Port 0 Wr Data (0)
DIO Port 0 Rd Data (1)
DIO Port 0 Wr Data (1)
DIO Port 0 Rd Data (2)
DIO Port 0 Wr Data (2)
DIO Port 0 Rd Data (3)
DIO Port 0 Wr Data (3)
DIO Port 1 Rd Data (0)
DIO Port 1 Wr Data (0)
DIO Port 1 Rd Data (1)
DIO Port 1 Wr Data (1)
DIO Port 1 Rd Data (2)
DIO Port 1 Wr Data (2)
DIO Port 1 Rd Data (3)
DIO Port 1 Wr Data (3)
DIO Port 1 WE
PFI 3 Wr Data
PFI <0..3> WE
PFI 3 Rd Data
PFI 1 Rd Data
PFI 1 Wr Data
PFI 2 Rd Data
PFI 2 Wr Data
PFI 0 Rd Data
PFI 0 Wr Data
4
User Data 1
User Command
User Command Commit
User Command Status
User Return
Initialization Done
User Error
User Command Idle
User Data 0
AI 1
AI 3
SPI Read Data
PLL Locked
Sync Clock
CLK IN
SPI Engine
Calibration
EEPROM
DAC SPI
ADC SPI
ADC SPI
ADT7408
Temperature
Sensor
DAC
OUT1 OUT2
CP
OUT4
CLK1
REF IN
AD9511
CLK2
SPI
VCXO
AC/DC
Gain
1, 2, 4x
Filters
AC/DC
Gain
1, 2, 4x
Filters
PLL Loop
Filter
Enable VCXO
Enable PLL
External Sample CLK
External Ref CLK
Channel Controls
Microcontroller
AI 1
AI 3
AI 1 Over Range
AI 3 Over Range
16
16
16
