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National Instruments NI 5422, Specifications

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©

 National Instruments Corporation

23

NI 5422 Specifications

Output Signal Characteristics (Continued)

Output Skew

Typical: 1 ns, maximum 2 ns. Skew between any 
two outputs on the DIGITAL DATA & CONTROL 
front panel connector.

—

Output 
Enable/Disable

Controlled through the software on all Data Output Signals 
and Control Signals collectively. When disabled, the outputs 
go to a high-impedance state.

—

Maximum 
Output 
Overload

–0.3 V to +3.9 V

—

Input Signal Characteristics (Includes DDC CLK IN and PFI<2..3>)

Signal Type

LVDS (Low-Voltage Differential Signal)

—

Input 
Differential 
Impedance

100 

Ω

—

Maximum 
Output 
Overload

–0.3 V to +3.9 V

—

Signal 
Characteristics

Minimum

Maximum

—

Differential 
Input Voltage

0.1 V

0.5 V

Input Common 
Mode Voltage

0.2 V

2.2 V

DDC CLK OUT

Clocking 
Format

Data outputs and markers change on the falling edge of 
DDC CLK OUT.

—

Frequency 
Range

Refer to the 

Sample Clock

 section for more information.

—

Duty Cycle

35% to 65%

—

Jitter

60 ps rms (typical)

—

Table 7.  

 (Continued)

Specification

Value

Comments

Summary of Contents for NI 5422

Page 1: ...ange without notice For the most recent NI 5422 specifications visit ni com manuals To access all of the NI 5422 documentation including the NI Signal Generators Getting Started Guide which contains functional descriptions of the NI 5422 signals navigate to Start Programs National Instruments NI FGEN Documentation Hot Surface If the NI 5422 has been in use it may exceed safe handling temperatures ...

Page 2: ...utput Voltage Characteristics Output Paths 1 The software selectable Main Output Path setting provides full scale voltages from 12 00 Vpk pk to 5 64 mVpk pk into a 50 Ω load NI FGEN uses either the Low Gain Amplifier or the High Gain Amplifier when the Main Output Path is selected depending on the Gain attribute 2 The software selectable Direct Path is optimized for IF applications and provides fu...

Page 3: ...ACcan be used 2 NI FGEN compensates for user specified resistive loads Minimum Value Maximum Value Direct 50 Ω 0 707 1 00 1 kΩ 1 35 1 91 Open 1 41 2 00 Low Gain Amplifier 50 Ω 0 00564 2 00 1 kΩ 0 0107 3 81 Open 0 0113 4 00 High Gain Amplifier 50 Ω 0 0338 12 0 1 kΩ 0 0644 22 9 Open 0 0676 24 0 Amplitude Resolution 3 digits Offset Range Span of 50 of Amplitude Range with increments 0 0028 of Amplitu...

Page 4: ...00 µV within 10 C of self calibration temperature 0 4 of Amplitude 0 05 of Offset 1 mV 0 C to 55 C All paths are calibrated for amplitude and gain errors The Low Gain and High Gain Amplifier Paths also are calibrated for offset errors Calibrated for high impedance load For the Direct Path Gain Accuracy 0 2 within 10 C of self calibration temperature Gain Accuracy 0 4 0 C to 55 C DC Offset Error 30...

Page 5: ...is shorted to ground indefinitely Waveform Summing The CH 0 output supports waveform summing among similar paths specifically the outputs of multiple NI 5422 signal generators can be connected directly together Frequency and Transient Response Analog Filter Software selectable 7 pole elliptical filter for image suppression Available on Low Gain Amplifier and High Gain Amplifier Paths Pulse Respons...

Page 6: ...and Flatness Low Gain Amplifier Path 1 10 100 Frequency MHz Flatness dB 0 1 2 4 3 1 Guaranteed Specification Typical 0 4 dB 0 3 dB 1 2 dB 3 4 dB 0 4 dB 0 4 dB 0 4 dB 0 3 dB 1 10 100 Frequency MHz Flatness dB 0 1 2 4 3 1 Guaranteed Specification Typical 0 3 dB 0 5 dB 3 4 dB 0 7 dB 0 7 dB 0 7 dB 0 7 dB 0 7 dB ...

Page 7: ... Gain Amplifier Path Figure 4 Pulse Response Low Gain Amplifier Path with a 50 Ω Load 1 10 100 Frequency MHz Flatness dB 0 1 2 4 3 1 Guaranteed Specification Typical 0 2 dB 0 6 dB 0 2 dB 1 1 dB 0 2 dB 1 1 dB 0 50 10 20 30 40 60 70 80 90 100 Time ns Amplitude V 0 4 1 6 1 2 0 8 0 4 0 2 0 2 0 1 6 1 2 0 8 ...

Page 8: ...ons Function Path Disable the Analog Filter for square ramp and triangle functions Direct Low Gain Amplifier High Gain Amplifier Sine 80 MHz 80 MHz 43 MHz Square Not Recommended 50 MHz 25 MHz Ramp Not Recommended 10 MHz 10 MHz Triangle Not Recommended 10 MHz 10 MHz Frequency MHz Sine Amplitude Vpp into 50 Ω 0 2 4 6 8 10 14 12 0 20 40 60 80 43 MHz Not Recommended Recommended Operation ...

Page 9: ...armonic distortion SFDR with harmonics at low amplitudes is limited by a 148 dBm Hz noise floor All values are typical and include aliased harmonics Direct Low Gain Amplifier High Gain Amplifier 1 MHz 70 dBc 65 dBc 66 dBc 5 MHz 70 dBc 65 dBc 58 dBc 10 MHz 70 dBc 65 dBc 52 dBc 20 MHz 63 dBc 64 dBc 49 dBc 30 MHz 57 dBc 60 dBc 43 dBc 40 MHz 48 dBc 53 dBc 39 dBc 50 MHz 48 dBc 53 dBc 60 MHz 47 dBc 52 d...

Page 10: ...dBFS 80 dBFS 77 dBFS 30 MHz 73 dBFS 71 dBFS 68 dBFS 40 MHz 48 dBFS 58 dBFS 55 dBFS 50 MHz 48 dBFS 53 dBFS 60 MHz 47 dBFS 52 dBFS 70 MHz 47 dBFS 52 dBFS 80 MHz 41 dBFS 52 dBFS AverageNoise Density Path Amplitude Range Average Noise Density Average Noise Density at small amplitudes is limited by a 168 dBm Hz noise floor Vpk pk dBm dBm Hz dBFS Hz Direct 1 00 4 0 19 9 141 145 Low Gain 0 06 20 5 1 3 16...

Page 11: ...ure 6 10 MHz Single Tone Spectrum Direct Path 200 MS s Typical Note The noise floor in Figure 6 is limited by the measurement device Refer to the Average Noise Density specification 0 10 20 30 40 50 60 70 80 90 100 Frequency MHz 10 0 10 20 30 40 50 60 70 80 90 dBm ...

Page 12: ...gle Tone Spectrum Low Gain Amplifier Path 200 MS s Typical Note The noise floor in Figure 7 is limited by the measurement device Refer to the Average Noise Density specification 0 10 20 30 40 50 60 70 80 90 100 Frequency MHz 10 0 10 20 30 40 50 60 70 80 90 dBm ...

Page 13: ...9 Total Harmonic Distortion Low Gain Amplifier Path 0 1 1 10 100 Frequency MHz Total Harmonic Distortion dBc 90 80 70 60 50 40 30 67 dBc 49 dBc 44 dBc Guaranteed Specification Typical 0 1 1 10 100 Frequency MHz Total Harmonic Distortion dBc 90 80 70 60 50 40 30 60 dBc 45 dBc 45 dBc Guaranteed Specification Typical ...

Page 14: ...th Figure 11 Intermodulation Distortion 200 kHz Separation Typical 0 1 1 10 100 Frequency MHz Total Harmonic Distortion dBc 90 80 70 60 50 40 30 45 dBc Guaranteed Specification Typical 85 50 55 60 65 70 75 80 1 10 100 Frequency MHz Intermodulation Distortion dBc Low Gain High Gain Direct Path ...

Page 15: ...fication Value Comments Sources 1 Internal Divide by N N 1 2 Internal DDS based High Resolution 3 External CLK IN SMB front panel connector 4 External DDC CLK IN DIGITAL DATA CONTROL front panel connector 5 External PXI Star trigger backplane connector 6 External PXI_Trig 0 7 backplane connector Refer to the Onboard Clock section for more information about Internal Clock Sources 0 10 20 30 40 50 6...

Page 16: ...ource External Sample Clock duty cycle tolerance 40 to 60 DDC CLK IN 5 MS s to 200 MS s PXI Star Trigger 5 MS s to 105 MS s PXI_Trig 0 7 5 MS s to 20 MS s Sample Clock Delay Range and Resolution Sample Clock Source Delay Adjustment Range Delay Adjustment Resolution Divide by N 1 sample clock period 5 ps High Resolution 100 MHz 1 sample clock period Sample Clock Period 16 384 High Resolution 100 MH...

Page 17: ...h Resolution1 200 MS s 108 120 122 4 2 ps rms CLK IN2 116 130 143 1 1 ps rms PXI Star Trigger2 3 111 128 136 2 1 ps rms External Sample Clock Input Jitter Tolerance Cycle Cycle Jitter 150 ps Period Jitter 1 ns Sample Clock Exporting Exported Sample Clock Destinations 1 PFI 0 1 SMB front panel connectors 2 DDC CLK OUT DIGITAL DATA CONTROL front panel connector 3 PXI_Trig 0 6 backplane connector Exp...

Page 18: ...kplane connector 2 CLK IN SMB front panel connector The PLL Reference Clock provides the reference frequency for the phase locked loop Frequency Accuracy When using the PLL the Frequency Accuracy of the NI 5422 is solely dependent on the Frequency Accuracy of the PLL Reference Clock Source Lock Time 200 ms Frequency Range 5 MHz to 20 MHz in increments of 1 MHz Default of 10 MHz The PLL Reference C...

Page 19: ...SMB jack Direction Input Destinations 1 Sample Clock 2 PLL Reference Clock Frequency Range 5 MHz to 200 MHz Sample Clock Destination 5 MHz to 20 MHz PLL Reference Clock destination Input Voltage Range Sine wave 0 65 Vpk pk to 2 8 Vpk pk into 50 Ω 0 dBm to 13 dBm Square wave 0 2 Vpk pk to 2 8 Vpk pk into 50 Ω Maximum Input Overload 10 V Input Impedance 50 Ω Input Coupling AC ...

Page 20: ...Frequency Range DC to 200 MHz As an Input Trigger Destinations Start Trigger Maximum Input Overload 2 V to 7 V VIH 2 0 V VIL 0 8 V Input Impedance 1 kΩ As an Output Event Sources 1 Sample Clock divided by integer K 1 K 4 194 304 2 Sample Clock Timebase 200 MHz divided by integer M 4 M 4 194 304 3 PLL Reference Clock 4 Marker 5 Exported Start Trigger Out Start Trigger Output Impedance 50 Ω ...

Page 21: ...ed Maximum Output Overload 2 V to 7 V VOH Minimum 2 7 V open load 1 3 V 50 Ω load Outputdriversare 3 3 V TTL compatible Measured with a 1 m cable VOL Maximum 0 6 V open load 0 2 V 50 Ω load Rise Fall Time 20 to 80 2 0 ns Load of 10 pF Table 6 Continued Specification Value Comments ...

Page 22: ...nput 5 PFI 4 output 6 PFI 5 output Ground 23 pins Output Signal Characteristics Includes Data Outputs DDC CLK OUT and PFI 4 5 Signal Type LVDS Low Voltage Differential Signal Signal Characteristics Minimum Typical Maximum 1 Tested with 100 Ω differential load 2 Measured with 188143B 01 cable 3 Driver and receiver comply with ANSI TIA EIA 644 VOH 1 3 V 1 7 V VOL 0 8 V 1 0 V Differential Output Volt...

Page 23: ...mum Output Overload 0 3 V to 3 9 V Input Signal Characteristics Includes DDC CLK IN and PFI 2 3 Signal Type LVDS Low Voltage Differential Signal Input Differential Impedance 100 Ω Maximum Output Overload 0 3 V to 3 9 V Signal Characteristics Minimum Maximum Differential Input Voltage 0 1 V 0 5 V Input Common Mode Voltage 0 2 V 2 2 V DDC CLK OUT Clocking Format Data outputs and markers change on th...

Page 24: ...B front panel connectors 2 PFI 2 3 DIGITAL DATA CONTROL front panel connector 3 PXI_Trig 0 7 backplane connector 4 PXI Star trigger backplane connector 5 Software use function call 6 Immediate does not wait for a trigger Default Modes 1 Single 2 Continuous 3 Stepped 4 Burst Edge Detection Rising Minimum Pulse Width 25 ns Refer to ts1 at NI Signal Generators Help Devices NI 5422 NI PXI 5422 Trigger...

Page 25: ...in the Destinations specification of Table 9 Exported Trigger Delay 65 ns typical Refer to ts3 at NI Signal Generators Help Devices NI 5422 NI PXI 5422 Triggering Trigger Timing Exported Trigger Pulse Width 150 ns Refer to ts4 at NI Signal Generators Help Devices NI 5422 NI PXI 5422 Triggering Trigger Timing Table 9 Specification Value Comments Destinations 1 PFI 0 1 SMB front panel connectors 2 P...

Page 26: ... Skew Destination With Respect to Analog Output With Respect to Digital Data Output Refer to tm1 at NI Signal Generators Help Devices NI 5422 NI PXI 5422 Waveform Generation Marker Events PFI 0 1 2 Sample Clock Periods N A PFI 4 5 N A 2 ns PXI_Trig 0 6 2 Sample Clock Periods N A Jitter 40 ps rms typical Table 9 Continued Specification Value Comments ...

Page 27: ...de In Arbitrary Waveform mode a single waveform is selected from the set of waveforms stored in onboard memory and generated Arbitrary Sequence Mode In Arbitrary Sequence mode a sequence directs the NI 5422 to generate a set of waveforms in a specific order Elements of the sequence are referred to as segments Each segment is associated with a set of instructions The instructions identify which wav...

Page 28: ...Waveform Memory 4 194 048 Samples 16 776 960 Samples 134 217 472 Samples 268 435 200 Samples Condition One or two segments in a sequence Arbitrary Sequence Mode Maximum Waveforms 65 000 Burst trigger 8 000 262 000 Burst trigger 32 000 2 097 000 Burst trigger 262 000 4 194 000 Burst trigger 524 000 Condition One or two segments in a sequence Arbitrary Sequence Mode Maximum Segments in a Sequence 10...

Page 29: ...e the DC gain and offset The self calibration is initiated by the user through the software and takes approximately 90 seconds to complete External Calibration The External Calibration calibrates the VCXO voltage reference DC gain and offset Appropriate constants are stored in nonvolatile memory Calibration Interval Specifications valid within two years of External Calibration Warm up Time 15 minu...

Page 30: ...r 50 Ωtermination 200 MS s High Resolution Sample Clock Digital Pattern enabled and terminated Sample Clock routed to PFI 0 and terminated Overload Operation occurs when CH 0 is shorted to ground 5 VDC Refer to Figure 13 2 7 A 12 VDC 0 46 A 0 46 A 12 VDC 0 01 A 0 01 A Total Power 12 2 W 5 V 5 V Current 25 7 W Frequency MHz Sine Amplitude Vpp into 50 Ω 0 2 4 6 8 10 12 0 10 20 30 40 50 60 70 80 2 6 ...

Page 31: ...ng interfaces for many development environments Application Software NI FGEN provides programming interfaces for the following application development environments LabVIEW LabWindows CVI Measurement Studio Microsoft Visual C C Microsoft Visual Basic Borland C C Interactive Control and Configuration software National Instruments provides several options for interactively controlling and configuring...

Page 32: ...d IEC 60068 2 2 Operating Relative Humidity 10 to 90 noncondensing Meets IEC 60068 2 56 Storage Relative Humidity 5 to 95 noncondensing Meets IEC 60068 2 56 Operating Shock 30 g half sine 11 ms pulse Meets IEC 60068 2 27 Test profile developed in accordance with MIL PRF 28800F Spectral and jitter specifications could degrade Storage Shock 50 g half sine 11 ms pulse Meets IEC 60068 2 27 Test profil...

Page 33: ... 1 For UL and other safety certifications refertotheproduct label or to ni com certification search by model number or product line and click the appropriate link in the Certification column Emissions EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Immunity EN 61326 1997 A2 2001 Table 1 Up to 4 mVpp noise about 44 dBm may be present on the output during the conducted immunity test Use of the pro...

Page 34: ...easures to reduce the interference This product meets the essential requirements of applicable European Directives as amended for CE marking as follows Low Voltage Directive safety 73 23 EEC Electromagnetic Compatibility Directive EMC 89 336 EEC Note Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product v...

Page 35: ... triggerinput sample clock output exported trigger output and PLL reference clock output SMB jack DIGITAL DATA CONTROL Digital data output trigger input exported trigger output markers external sample clock input and sample clock output 68 pin VHDCI female receptacle Front Panel LED Indicators Label Function For more information refer to the NI Signal Generators Help ACCESS LED The ACCESS LED indi...

Page 36: ...roduct supports calibration you can obtain the calibration certificate for your product at ni com calibration National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also has offices located around the world to help address your support needs For telephone support in the United States create your service request at ni com ...

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