National Instruments NI 5421 s Specifications Download Page 34

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NI 5421 Specifications

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Physical

Table 17.

Specification

Value

Comments

Dimensions

NI PXI-5421

NI PCI-5421

—

3U, One Slot,

PXI/cPCI Module

2.0

13.0

21.6 cm

(0.8

5.1

8.5 inches)

34.07

10.67

2.03 cm

(13.4

4.20

0.8 inches)

Weight

345 g (12.1 oz)

419 g (14.8 oz)

—

Front Panel Connectors

Label

Function(s)

Connector Type

—

CH 0

Analog Output

SMB (jack)

CLK IN

Sample clock input and PLL
reference clock input.

SMB (jack)

PFI 0

Marker output, trigger input,
sample clock output,
exported trigger output, and
PLL reference clock output.

SMB (jack)

PFI 1

Marker output, trigger input,
sample clock output,
exported trigger output, and
PLL reference clock output.

SMB (jack)

DIGITAL
DATA &
CONTROL

Digital data output, trigger
input, exported trigger
output, markers, external
sample clock input, and
sample clock output.

68-pin VHDCI female
receptacle

Summary of Contents for NI 5421 s

Page 1: ...ifications visit ni com manuals To access all the NI 5421 documentation including the NI Signal Generators Getting Started Guide which contains functional descriptions of the NI 5421 signals navigate...

Page 2: ...e selectable Main Output Path setting provides full scale voltages from 12 00 Vpk pk to 5 64 mVpk pk into a 50 load NI FGEN uses either the Low Gain Amplifier or the High Gain Amplifier when the Main...

Page 3: ...theDACcan be used 2 NI FGEN compensates for user specified resistive loads Minimum Value Maximum Value Direct 50 0 707 1 00 1 k 1 35 1 91 Open 1 41 2 00 Low Gain Amplifier 50 0 00564 2 00 1 k 0 0107 3...

Page 4: ...ration temperature 0 4 of Amplitude 0 05 of Offset 1 mV 0 C to 55 C All paths are calibrated for amplitude and gain errors The Low Gain and High Gain Amplifier Paths also are calibrated for offset err...

Page 5: ...nal generators can be connected together Frequency and Transient Response Bandwidth 43 MHz Measured at 3 dB Digital Interpolation Filter Software selectable Finite Impulse Response FIR filter Availabl...

Page 6: ...esponse Low Gain Amplifier Path 50 Load 1 0M 10 0M 48 0M 10 0 9 0 6 0 8 0 5 0 7 0 3 0 2 0 1 0 0 0 1 0 2 0 Frequency Hz dB 4 0 0 3 dB 0 4 dB 0 4 dB 0 4 dB 0 6 dB 0 4 dB Guaranteed Specification Typical...

Page 7: ...er Sine 43 MHz 43 MHz 43 MHz Square Not Recommended 25 MHz 12 5 MHz Ramp Not Recommended 5 MHz 5 MHz Triangle Not Recommended 5 MHz 5 MHz Spectral Characteristics Signal to Noise and Distortion SINAD...

Page 8: ...c 20 MHz 60 dBc 57 dBc 42 dBc 30 MHz 73 dBc 73 dBc 74 dBc 40 MHz 76 dBc 73 dBc 74 dBc 43 MHz 78 dBc 75 dBc 59 dBc Spurious Free Dynamic Range SFDR without Harmonics Path Amplitude 1 dBFS Measured from...

Page 9: ...dBc 55 dBc 10 MHz 65 dBc 61 dBc 46 dBc 20 MHz 55 dBc 53 dBc 30 MHz 50 dBc 48 dBc 40 MHz 48 dBc 46 dBc 43 MHz 47 dBc 45 dBc 0 C to 55 C Total Harmonic Distortion THD Path Amplitude 1 dBFS Includes the...

Page 10: ...gh Gain 4 16 0 71 130 146 0 High Gain 12 25 6 213 120 145 6 Intermodulation Distortion IMD Path Each tone is 7 dBFS All values are typical Direct Low Gain Amplifier High Gain Amplifier 10 2 MHz and 11...

Page 11: ...Direct Path 100 MS s Interpolation Factor Set to 4 Note The noise floor in Figure 3 is limited by the measurement device Refer to the Average Noise Density specification 0 0 25 0M 50 0M 75 0M 100 0M 1...

Page 12: ...h 100 MS s Interpolation Factor Set to 4 Note The noise floor in Figure 4 is limited by the measurement device Refer to the Average Noise Density specification 0 0 25 0M 50 0M 75 0M 100 0M 125 0M 150...

Page 13: ...Path 2 Tone Spectrum Typical Note The noise floor in Figure 5 is limited by the measurement device Refer to the Average Noise Density specification 0 0 25 0M 50 0M 75 0M 100 0M 125 0M 150 0M 175 0M 20...

Page 14: ...ernal RTSI 0 7 Refer to the Onboard Clock section for more information about Internal Clock Sources Sample Rate Range and Resolution Sample Clock Source Sample Rate Range Sample Rate Resolution Divide...

Page 15: ...105 MS s 12 5 MS s to 105 MS s 2 25 MS s to 210 MS s 10 MS s to 100 MS s 4 40 MS s to 400 MS s 10 MS s to 50 MS s 8 80 MS s to 400 MS s Sample Clock Delay Range and Resolution Sample Clock Source Dela...

Page 16: ...ecification is valid when the Sample Clock Source is locked to PXI_CLK10 100 Hz 1 kHz 10 kHz NI PXI 5421 Divide by N 107 121 137 1 2 ps rms NI PCI 5421 Divide by N 110 127 137 2 0 ps rms High Resoluti...

Page 17: ...dividedbyinteger K 1 K 4 194 304 Exported Sample Clock Destinations Maximum Frequency Jitter Typical Duty Cycle PFI 0 1 105 MHz PFI 0 6 ps rms PFI 1 12 ps rms 25 to 65 DDC CLK OUT 105 MHz 40 ps rms 4...

Page 18: ...Frequency Accuracy When using the PLL the Frequency Accuracy of the NI 5421 is solely dependent on the Frequency Accuracy of the PLL Reference Clock Source Lock Time Typical 70 ms Maximum 200 ms Freq...

Page 19: ...s 1 Sample Clock 2 PLL Reference Clock Frequency Range 1 MHz to 105 MHz Sample Clock destination and sine waves 200 kHz to 105 MHz Sample Clock destination and square waves 5 MHz to 20 MHz PLL Referen...

Page 20: ...C to 105 MHz As an Input Trigger Destinations Start Trigger Maximum Input Overload 2 V to 7 V VIH 2 0 V VIL 0 8 V Input Impedance 1 k As an Output Event Sources 1 Sample Clock divided by integer K 1 K...

Page 21: ...fications VOH Minimum 2 9 V open load 1 4 V 50 load Outputdriversare 3 3 V TTL compatible Measured with a 1 m cable VOL Maximum 0 2 V open load 0 2 V 50 load Rise Fall Time 20 to 80 2 0 ns Load of 10...

Page 22: ...6 PFI 5 output Ground 23 pins Output Signal Characteristics Includes Data Outputs DDC CLK OUT and PFI 4 5 Signal Type LVDS Low Voltage Differential Signal Signal Characteristics Minimum Typical Maxim...

Page 23: ...Maximum Output Overload 0 3 V to 3 9 V Input Signal Characteristics Includes DDC CLK IN and PFI 2 3 Signal Type LVDS Low Voltage Differential Signal Input Differential Impedance 100 Maximum Output Ove...

Page 24: ...Sources 1 PFI 0 1 SMB front panel connectors 2 PFI 2 3 DIGITAL DATA CONTROL front panel connector 3 NI PXI 5421 PXI_Trig 0 7 backplane connector NI PCI 5421 RTSI 0 7 4 NI PXI 5421 PXI Star trigger ba...

Page 25: ...mple Clock Periods 110 ns Delay from Start Trigger to Digital Data Output 40 Sample Clock periods 110 ns Trigger Exporting Exported Trigger Destinations A signal used as a trigger can be routed out to...

Page 26: ...on must be placed at an integer multiple of four samples Width 150 ns Refer to tm2 at NI Signal Generators Help Devices NI 5421 NI bus 5421 Waveform Generation Marker Events Skew Destination With Resp...

Page 27: ...Arbitrary Sequence mode Arbitrary Waveform Mode In Arbitrary Waveform mode a single waveform is selected from the set of waveforms stored in onboard memory and generated Arbitrary Sequence Mode In Arb...

Page 28: ...ry Sequence Mode Maximum Waveform Memory 4 194 120 Samples 16 777 008 Samples 134 217 520 Samples Condition One or two segments in a sequence Arbitrary Sequence Mode Maximum Waveforms 65 000 Burst tri...

Page 29: ...5 seconds to complete External Calibration The External Calibration calibrates the VCXO voltage reference DC gain and offset Appropriate constants are stored in nonvolatile memory Calibration Interval...

Page 30: ...NI FGEN provides programming interfaces for the following application development environments LabVIEW LabWindows CVI Measurement Studio Microsoft Visual C C Microsoft Visual Basic Borland C C Soft F...

Page 31: ...68 2 1 and IEC 60068 2 2 Operating Relative Humidity 10 to 90 noncondensing Meets IEC 60068 2 56 Storage Relative Humidity 5 to 95 noncondensing Meets IEC 60068 2 56 Operating Shock 30 g half sine 11...

Page 32: ...ating Temperature 0 C to 45 C Meets IEC 60068 2 1 and IEC 60068 2 2 Storage Temperature 25 C to 85 C Meets IEC 60068 2 1 and IEC 60068 2 2 Operating Relative Humidity 10 to 90 noncondensing Meets IEC...

Page 33: ...le 1 EMC EMI CE C Tick and FCC Part 15 Class A Compliant Notes 1 This device is not intended for and is restricted from use in residential areas 2 For EMC compliance operate this device with shielded...

Page 34: ...or Type CH 0 Analog Output SMB jack CLK IN Sample clock input and PLL reference clock input SMB jack PFI 0 Markeroutput triggerinput sample clock output exported trigger output and PLL reference clock...

Page 35: ...tors Help ACCESS LED The ACCESS LED indicates the status of the PCI bus and the interface from the NI 5421 to the controller ACTIVE LED The ACTIVE LED indicates the status of the onboard generation ha...

Page 36: ...libration certificate for your product at ni com calibration National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also ha...

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