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National Instruments Corporation
9
NI 5412 Specifications
System Phase Noise and Jitter (10 MHz Carrier)
Sample Clock
Source
System Phase Noise
Density
(dBc/Hz) Offset
System Output Jitter
(Integrated from
100 Hz to 100 kHz)
1. High-
Resolution
specifications
vary with
Sample Rate.
2. All values are
typical.
100 Hz
1 kHz
10 kHz
NI PXI-5412
–100
–118
–120
<6 ps rms
NI PCI-5412
–90
–110
–120
<7 ps rms
External
Sample Clock
Input Jitter
Tolerance
Cycle-Cycle Jitter ±300 ps
Period Jitter ±1 ns
—
Sample Clock Exporting
Exported
Sample Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
2.
NI PXI-5412
: PXI_Trig<0..6> (backplane connector)
NI PCI-5412
: RTSI<0..6>
Exported Sample
Clocks can be
divided by integer
K
(1
≤
K
≤
4,194,304).
Exported
Sample Clock
Destinations
Maximum Frequency
Duty Cycle
—
PFI<0..1>
105 MHz
25% to 65%
NI PXI-5412
PXI_Trig<0..6>
20 MHz
—
NI PCI-5412
RTSI<0..6>
20 MHz
—
Table 2.
(Continued)
Specification
Value
Comments
