Chapter 3
Device Overview and Theory of Operation
©
National Instruments Corporation
3-15
♦
NI PCI-4472 and NI PCI-4474
The NI PCI-4472 and NI PCI-4474 can use either its internal DDS
timebase or a timebase received over the RTSI bus. If you configure the
NI PCI-4472 or NI PCI-4474 to use the internal timebase, you can program
the NI PCI-4472 or NI PCI-4474 to drive its internal timebase over the
RTSI bus to another NI PCI-4472 or NI PCI-4474 that you program to
receive this timebase signal. The default configuration at startup is to use
the internal timebase without driving the RTSI bus timebase signal. This
timebase is software selectable.
On the NI 447
X
, the ratio between the oversample (
f
os
) clock and the
sample rate (
f
s
) can have one of two possible values, depending on the
sample rate. Table 3-1 shows the possible values.
The highest possible oversample frequency for the NI 447
X
occurs at either
f
s
= 51.2 kS/s or
f
s
= 102.4 kS/s. In both cases, the oversample rate is
slightly faster than 13.1 MHz.
The ADCs on the NI 447
X
operate at half the oversample clock.
Most delta-sigma converters, including those on the NI 447
X
, require a very
steady frequency for the oversample clock. The DDS chip on the NI 447
X
has good frequency characteristics and easily fulfills this need. However,
arbitrarily changing frequencies, such as those from encoders, generally do
not work well with delta-sigma ADCs. For this reason, the NI 447
X
and
other National Instruments DSA products do not support external clocking
from arbitrary signal sources.
The NI 447
X
SYNC Pulse
As discussed in the
Delta-Sigma ADCs and the Oversample Clock
section,
the oversample clock is many times faster than the actual acquisition rate
of the NI 447
X
. Using the concepts described in that section, you can share
the oversample clock between two or more NI 447
X
modules. This sharing
guarantees that both modules sample at the same frequency and that there
will be no drift between their acquisitions. However, oversample-clock
sharing does not guarantee that the samples on both modules are acquired
Table 3-1.
Relationship between the Sample Rate and Oversample Clock
Sample Rate
Oversample Clock
f
s
≤
51.2 kS/s
f
os
= 256
×
f
s
f
s
> 51.2 kS/s
f
os
= 128
×
f
s
