myRIO-1950 JTAG Instructions
This document is intended to give instructions on how to use the myRIO-1950 JTAG port for
lead users. This is not intended for the general public and should be distributed with caution.
Using the JTAG port may cause permanent damage to the myRIO-1950 if improperly used.
1.0 General JTAG specifications
Logic Level:
1.8V
1
Max JTAG Frequency:
10Mhz
Devices in JTAG Chain
2
:
1st) Zynq PS (Arm processor)
2nd) Zynq PL (FPGA Fabric)
3rd) LCMXO2-640 CPLD
2
Number of JTAG Instruction Registers:
Zynq PS = 4
Zynq PL = 6
CPLD = 8
1
NOTE that the JTAG pins are ESD sensitive. Additionally they may be damaged if overvoltage
above 1.8V. Be sure to attach the VREF pin of the JTAG programmer properly. Do not force the
JTAG programmer to use any voltage other than 1.8V on its IO.
2
CAUTION: The CPLD is not intended for customer access over JTAG. If you modify the CPLD your
myRIO-1950 will no longer function properly. Do not attempt to program the CPLD.
