Chapter 3
Timing Diagrams
©
National Instruments Corporation
3-19
Figure 3-16.
Level-ACK Input Timing Diagram
Note
With REQ-edge latching enabled (default), the REQ edge determines when data is
latched. Input data valid has to be held before the active-going REQ edge a minimum of
t
rdi
ns. With REQ edge disabled, input data valid has to be held
t
adi
after the next
active-going ACK signal edge is asserted.
Parameter
Description
Minimum
Maximum
Input Parameters
t
rr*
REQ pulse width
75
—
t
r*r
REQ inactive duration
75
—
t
ar
ACK to next REQ
0
—
t
dir(1)
Input data setup to REQ active
(with REQ-edge latching)
0
—
t
rdi
Input data hold from REQ active
(with REQ-edge latching)
10
—
t
dir(2)
Input data setup to REQ
(with REQ-edge latching disabled)
0
—
t
adi
Input data hold from ACK
(with REQ-edge latching disabled)
0
—
Output Parameters
t
aa*
ACK pulse width
225
—
t
ra*
REQ to ACK inactive
100
200
All timing values are in nanoseconds.
REQ
Input Data Valid
(REQ-edge
Latching)
Input Data Valid
(REQ-edge
Latching Disabled)
t
r*r
t
ra*
t
dir(2)
t
adi
t
ar
t
aa*
t
rr*
t
rdi
t
dir(1)
ACK
ACK and REQ are shown as active high.