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DAQArb

5411

User Manual

High-Speed Arbitrary Waveform Generator

DAQArb 5411 User Manual

June 1997 Edition

Part Number 321558A-01

Summary of Contents for DAQArb 5411

Page 1: ...DAQArbTM 5411 User Manual High Speed Arbitrary Waveform Generator DAQArb 5411 User Manual June 1997 Edition Part Number 321558A 01 Copyright 1997 National Instruments Corporation All Rights Reserved...

Page 2: ...76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 034...

Page 3: ...R INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contrac...

Page 4: ...National Instruments Application Software 1 3 NI DAQ Driver Software 1 4 Optional Equipment 1 5 Cabling 1 5 Unpacking 1 6 Chapter 2 Installation and Configuration Installation 2 1 Hardware Configurat...

Page 5: ...ution and Lookup Memory 4 10 Frequency Hopping and Sweeping 4 11 Triggering 4 11 Trigger Sources 4 11 Modes of Operation 4 12 Single Trigger Mode 4 12 Continuous Trigger Mode 4 13 Stepped Trigger Mode...

Page 6: ...nments 3 5 Figure 3 5 SHC50 68 68 Pin Connector Pin Assignments 3 7 Figure 4 1 DAQArb 5411 Block Diagram 4 1 Figure 4 2 Waveform Data Path Block Diagram 4 3 Figure 4 3 Waveform Memory Architecture 4 4...

Page 7: ...4 22 Figure 4 21 Master Slave Configurations for Phase Locking 4 23 Figure 4 22 Analog Filter Correction 4 25 Figure 4 23 Digital Pattern Generator Data Path 4 26 Figure 4 24 Digital Pattern Generati...

Page 8: ...ur DAQArb 5411 Chapter 3 Signal Connections describes the I O connectors signal connections and digital interface to the DAQArb 5411 Chapter 4 Arb Operation describes how to use your DAQArb 5411 Appen...

Page 9: ...cept This font also denotes text from which you supply the appropriate word or value as in Windows 3 x italic monospace Italic text in this font denotes that you must enter the appropriate words or va...

Page 10: ...e output impedances of 50 and 75 Output attenuation levels from 0 to 73 dB Phase locked loop PLL synchronization to external clocks Sampling rate of 610 S s to 40 MS s 2 000 000 sample onboard wavefor...

Page 11: ...will need the following One of the following DAQArb 5411 devices PCI 5411 AT 5411 DAQArb 5411 User Manual NI DAQ for PC compatibles version 5 0 or later One of the following software packages and doc...

Page 12: ...1 devices can use only the Advanced Analog Output VIs in LabVIEW for analog output functions LabWindows CVI features interactive graphics a state of the art user interface and uses the ANSI standard C...

Page 13: ...tional Instruments DAQ hardware NI DAQ is not packaged with accessory products NI DAQ has an extensive library of functions that you can call from your application programming environment Whether you...

Page 14: ...r National Instruments catalogue or web site or call the office nearest you Cabling The following list gives recommended part numbers for cables that you can use with your 5411 device BNC male to BNC...

Page 15: ...device take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the anti static package to a metal part of your computer chassis before removing the d...

Page 16: ...DAQArb 5411 and other hardware Before installing your 5411 device consult your PC user manual or technical reference manual for specific instructions and warnings Follow these general instructions to...

Page 17: ...MB You can upgrade to a 16 MB memory module to store large waveform buffers directly on the card Perform the following steps to install the new memory module 1 Turn off the computer and remove the to...

Page 18: ...is chapter describes the I O connectors signal connections and digital interface to the DAQArb 5411 I O Connector The DAQArb 5411 has four connectors three SMB connectors and a 50 pin mini SCSI type c...

Page 19: ...ther load the levels are where Vout is the maximum output voltage level RL is the load impedance in ohms and RO is the output impedance on the DAQArb 5411 By default RO 50 but the software can also se...

Page 20: ...m a comparator connected to the analog waveform and is intended to be used when the waveform is a sine function The SYNC output will provide a meaningful waveform only when you are generating a sine w...

Page 21: ...l clock to the best accuracy possible For more information on PLL operation refer to Chapter 4 Arb Operation Dig Out Connector Dig Out is a 16 bit digital I O connector that contains the 16 bit digita...

Page 22: ...ptions used on the DAQArb 5411 digital output connector 50 1 26 2 27 3 28 4 29 5 30 6 31 7 32 8 33 9 34 10 35 11 36 12 37 13 38 14 39 15 40 16 41 17 42 18 43 19 44 20 45 21 46 22 47 23 48 24 49 DGND P...

Page 23: ...n set up at any point in the waveform being generated You can use this signal to synchronize or trigger other devices at a certain time within waveform generation NC Not connected PA 0 15 Output Digit...

Page 24: ...15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 26 PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7...

Page 25: ...setting Output impedance remains unchanged from previous setting Digital pattern generation is disabled When you reset the board using NI DAQ or any application software calling NI DAQ your DAQArb is...

Page 26: ...and Play protocols for assigning resources to the device and providing drivers for the data and address bus that are local to the device The waveform sequencer performs multiple Data Path ISA PCI Chan...

Page 27: ...mode you can define waveforms as multiple buffers You can link and loop these buffers in any order you desire This mode has more features and is more flexible than DDS mode Note If you use Virtual Ben...

Page 28: ...h is 610 35 Hz Note For DDS mode you should always keep the update rate at 40 MHz Doing this will yield the best performance of the combination of DDS digital filter DAC and analog filter Arb Mode The...

Page 29: ...eed You can upgrade to an 8 million sample waveform memory by installing the optional 16 MB memory module See Chapter 2 Installation and Configuration for more information on the memory module As show...

Page 30: ...es also referred to as a waveform segment You can load multiple buffers in the memory on DAQArb 5411 To generate these buffers you have to prepare a staging list also known as a sequence list which co...

Page 31: ...gure 4 5 shows waveform staging in hardware The instruction FIFO contains the staging list which the DAQArb 5411 sequencer reads for waveform generation Waveform Sample A Waveform Buffer Segment 1 Wav...

Page 32: ...e will automatically use the true size of that buffer Buffer loops Specifies the number of times that buffer has to be looped The maximum number of loops possible is 65 535 Marker offset Specifies whe...

Page 33: ...rol an analog frequency source from a single reference clock frequency This technique provides high frequency accuracy and resolution temperature stability wideband tuning and very fast and phase cont...

Page 34: ...nding just one instruction You can use DDS mode for very fine frequency resolution function generation You can generate sine waves of up to 16 MHz with a frequency resolution of 10 0 mHz Because this...

Page 35: ...uency resolution Fc 2N 40 x 106 232 9 31322 mHz For example if you need to generate a frequency of 10 MHz then the FCW is 232 10E6 40E6 which equals 1 073 741 824 If you need to generate a frequency o...

Page 36: ...ode has a different instruction set than Arb mode Note The minimum time that a frequency should be generated is at least 2 s Therefore the maximum hop rate from one frequency to the other frequency is...

Page 37: ...for both arb and DDS modes Single Trigger Mode The waveform you describe in the sequence list is generated only once by going through the entire staging list Only one trigger is required to start the...

Page 38: ...e 1 f1 specifies the sine frequency to be generated for time T1 f2 and T2 for stage 2 and so on If there are four stages in the staging list then f4 will be generated continuously until the waveform g...

Page 39: ...st stage is generated Then the device waits for the next trigger signal On the next trigger the waveform described by the second stage is generated and so on Once the staging list is exhausted the wav...

Page 40: ...trigger is received the waveform described by the first stage is generated until another trigger is received At the next trigger the buffer of the previous stage is completed before the waveform descr...

Page 41: ...ou can define this TTL level trigger output signal at any position in the waveform buffer You can place a marker in every stage however only one marker per stage is allowed You can specify a marker by...

Page 42: ...at positions 8 15 Figure 4 16 shows an analog waveform being generated at one connector and a marker being generated at another I O connector Point A shows a marker generated for requested positions...

Page 43: ...on offset This fine tuning of gain and offset is done using separate DACs The output from the 10 dB attenuator is then fed to the main amplifier which can provide 5 V levels into 50 An output relay ca...

Page 44: ...nt to the SYNC connector through a hysteresis buffer and a 50 series resistor to provide reverse termination of reflected pulses You can use the SYNC output as a very high frequency resolution softwar...

Page 45: ...vel to 2 5 V into a terminated load use the following formula Attenuation 20 log10 2 5 5 6 020 dB Note You can change the output attenuation at any time during waveform generation Output Impedance As...

Page 46: ...justment to the waveform before the attenuation chain You can adjust the pre attenuation offset provided you have at least 10 dB of attenuation switched in With a terminated load you get a 2 5 V offse...

Page 47: ...red by a phase comparator running at 1 MHz The error signal is filtered out by the loop filter and sent to the control pin of the VCXO to complete the loop Figure 4 20 Phase Locked Loop PLL Architectu...

Page 48: ...a DAQArb set the source for the RTSI clock line to board clock for NI DAQ software and internal for LabVIEW 2 Set up the slave devices so that the PLL reference source is set to the RTSI clock line 3...

Page 49: ...ggered at the same time and get phase and frequency locked Note If two or more DAQArb devices are running in Arb mode and are locked to each other using the same reference clock then you will see a ma...

Page 50: ...ector This digital data is first synchronized to the sample clock and then buffered and sent to the connector through a 80 series resistor The sample clock is also buffered and sent to the digital con...

Page 51: ...to test digital devices such as serial and parallel DACs and to emulate protocols Note At computer power up and reset pattern generation is disabled Figure 4 24 shows the timing waveforms for digital...

Page 52: ...ignals to the RTSI switch Figure 4 25 DAQArb 5411 RTSI Trigger Lines and Routing For phase locking to other boards as a master the 5411 sends an onboard 20 MHz signal to the RTSI Osc line as a Board C...

Page 53: ...ments On the DAQArb 5411 NI DAQ automatically makes these adjustments by retrieving predetermined constants from the onboard EEPROM calculating correction values and writing those values to the CalDAC...

Page 54: ...herwise stated The operating temperature range is 0 to 50 C Analog Output Number of channels 1 Resolution 12 bits Maximum update rate 40 MHz DDS accumulator 32 bits Frequency range Arb 40 MS s Sine 16...

Page 55: ...dance 50 or greater Output enable Software switchable Protection Short circuit protected Sine Spectral Purity Harmonic products and spurious up to 1 MHz 60 dBc up to 16 MHz 35 dBc Phase noise 105 dBc...

Page 56: ...es min multiples of eight samples DDS mode 16 384 samples exact Max segments in waveform memory 5 000 Arb mode only Segment linking instruction FIFO Arb mode 292 links DDS mode 340 links Segment loopi...

Page 57: ...width Td1 20 ns min Trigger to waveform output Arb mode delay Td2 76 sample clocks 38 ns max Trigger to waveform output DDS mode delay Td2 28 sample clocks 150 ns max RTSI Trigger lines 7 Clock lines...

Page 58: ...z max Resolution 16 bits Sample clock logic TTL Clock pulse HIGH time 25 ns fixed for clock interval counts 1 PCLK to pattern data output time Tco 1 ns max Digital pattern logic TTL Logic level output...

Page 59: ...s Amplitude 1 Vpk pk level 5 Vpk pk Internal clock Frequency 40 MHz Initial accuracy 5 ppm Temperature stability 0 to 5 C 25 ppm Aging 1 year 5 ppm Mechanical Connectors ARB output SMB SYNC output SMB...

Page 60: ...date clock fc is twice that of the bandwidth of the signal of interest it is very difficult to design an analog filter that will reject the images above the passband and also get maximum output bandwi...

Page 61: ...filter roll off easily rejects any images from the output spectrum This behavior can be seen in the frequency domain representation from Figure B 2 and in the time domain representation from Figure B...

Page 62: ...ems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS...

Page 63: ...d your software to obtain support Telephone Fax Australia 03 9879 5166 02 9874 4455 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086...

Page 64: ..._______________________________________________ _______________________________________________________________________________ National Instruments hardware product model __________ Revision ________...

Page 65: ...____________________________________________ Base I O address of other boards _____________________________________________________ DMA channels of other boards _______________________________________...

Page 66: ..._________________________________________________ _______________________________________________________________________________ ______________________________________________________________________...

Page 67: ...AQArb 5411 User Manual Glossary Numbers Symbols percent positive of or plus negative of or minus plus or minus per degree ohm 5V 5 V output signal Prefix Meaning Value p pico 10 12 n nano 10 9 micro 1...

Page 68: ...s not generator restricted to standard waveforms such as sine or square ASIC Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of...

Page 69: ...uter bus C C Celsius CalDAC calibration DAC clock hardware component that controls timing for reading from or writing to groups continuous trigger mode repeats a staging list until waveform generation...

Page 70: ...in DDS functionality to generate very high frequency resolution standard waveforms default setting a default parameter value recorded in the driver In many cases the default input of a control is a ce...

Page 71: ...til the data can be retrieved into system memory a process that requires the servicing of interrupts and often the programming of the DMA controller This process can take several milliseconds in some...

Page 72: ...puter signal indicating that the CPU should suspend its current task to service a designated activity interrupt level the relative priority at which a device can interrupt I O input output the transfe...

Page 73: ...unwanted high frequency contents form the signal LSB least significant bit M m meters M 1 Mega the standard metric prefix for 1 million or 106 when used with units of measure such as volts and hertz 2...

Page 74: ...National Institute of Standards and Technology noise an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights sold...

Page 75: ...put peak to peak a measure of signal amplitude the difference between the highest and lowest excursions of the signal pipeline a high performance processor structure in which the completion of an inst...

Page 76: ...root mean square the square root of the average value of the square of the instantaneous signal amplitude a measure of signal amplitude ROM read only memory RTSI bus real time system integration bus t...

Page 77: ...DDS mode specifies the frequency to be generated of the waveform in the lookup memory and the time for which that frequency has to be generated staging list a buffer that contains linking and looping...

Page 78: ...andalone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program W waveform multiple voltage readings taken at a specific sampling rate wav...

Page 79: ...and resolution 4 4 to 4 5 Arb operation analog filter correction 4 24 to 4 25 analog output 4 18 to 4 21 analog output and SYNC out block diagram 4 18 output attenuation 4 19 to 4 20 output enable 4 2...

Page 80: ...al clock A 6 configuration See installation and configuration connectors See I O connector SHC50 68 50 pin cable connector continuous trigger mode Arb mode 4 14 DDS mode 4 14 overview 4 13 customer co...

Page 81: ...de 4 10 to 4 11 FTP support C 1 H hardware configuration 2 2 I installation and configuration hardware configuration 2 2 installation procedure 2 1 to 2 2 installing optional memory module 2 2 unpacki...

Page 82: ...rements for getting started 1 2 reset conditions 3 8 RFU signal table 3 6 RTSI trigger lines 4 27 to 4 28 locking DAQArb 5411 to other National Instrument cards note 3 3 purpose and use 4 27 to 4 28 s...

Page 83: ...C 2 timing I O specifications A 3 transistor transistor logic TTL SYNC connector 3 3 trigger specifications digital trigger A 4 RTSI A 4 triggering 4 11 to 4 16 burst trigger mode 4 15 to 4 16 contin...

Page 84: ...eform memory Arb mode 4 3 architecture figure 4 4 overview 4 4 waveform sampling and interpolation B 1 to B 2 waveform segment 4 5 waveform size and resolution 4 4 to 4 5 minimum buffer size and resol...

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