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National Instruments Corporation
8-1
DAQ-STC Technical Reference Manual
8
Interrupt Control
8.1 Overview
This chapter describes the interrupt control module (ICM), its features, and the conditions that
cause interrupts. The ICM consists of two interrupt banks that can be routed to any two of the
eight open drain, interrupt output lines. The ICM allows using one or two interrupt channel
interfaces to the CPU. Interrupt group A handles the interrupts associated with the AITM, the
board-level interrupt input IRQ_IN0, and interrupts associated with general-purpose counter
0. Interrupt group B handles the interrupts associated with the AOTM, board-level interrupt
input IRQ_IN1, and interrupts associated with general-purpose counter 1.
The combined interrupt output of both interrupt groups can be enabled on the first two
interrupt lines as well. This allows pairing up to three pins externally to increase the sink
current capability. This is useful for buses such as the NuBus, which have a single-interrupt
line but high-current sink requirements.
Two additional independently controlled outputs from each of the two interrupt groups are
provided to simplify the interface for hardware acceleration of specific interrupt-driven tasks,
such as general-purpose counter/timer input using DMA instead of interrupts. The additional
independent interrupt outputs are called secondary interrupt outputs.
8.2 Features
The ICM has the following features:
•
Eight tri-statable interrupt lines with high-current output stages for direct interface to the
bus.
•
Two interrupt groups with individual channel selections. Both groups can share the same
interrupt channel.
•
Two external interrupt inputs for board-level interrupts generated outside the DAQ-STC.
•
18 internally generated interrupt sources relating to the AITM, AOTM, and GPCT
modules.
•
Two additional independently controlled outputs for each group allow an additional
mechanism for interrupt service.
