Chapter 3
Hardware Overview
PCI-6023E/6024E/6025E User Manual
3-6
©
National Instruments Corporation
Digital I/O
The PCI-6023E, PCI-6024, and PCI-6025E boards contain eight lines of
digital I/O (DIO<0..7>) for general-purpose use. You can individually
software-configure each line for either input or output. At system startup
and reset, the digital I/O ports are all high impedance.
The hardware up/down control for general-purpose counters 0 and 1 are
connected onboard to DIO6 and DIO7, respectively. Thus, you can use
DIO6 and DIO7 to control the general-purpose counters. The up/down
control signals are input only and do not affect the operation of the DIO
lines.
♦
PCI-6025E only:
The PCI-6025E board uses an 82C55A Programmable Peripheral Interface
to provide an additional 24 lines of digital I/O that represent three 8-bit
ports: PA, PB, PC. Each port can be programmed as an input or output port.
The 82C55A has three modes of operation: simple I/O (mode 0), strobed
I/O (mode 1), and bidirectional I/O (mode 2). In modes 1 and 2, the three
ports are divided into two groups: group A and group B. Each group has
eight data bits, plus control and status bits from Port C (PC). Modes 1 and
2 use handshaking signals from the computer to synchronize data transfers.
Refer to Chapter 4,
, for more detailed information.
Timing Signal Routing
The DAQ-STC chip provides a flexible interface for connecting timing
signals to other boards or external circuitry. Your board uses the RTSI bus
to interconnect timing signals between boards, and the Programmable
Function Input (PFI) pins on the I/O connector to connect the board to
external circuitry. These connections are designed to enable the board to
both control and be controlled by other boards and circuits.
There are a total of 13 timing signals internal to the DAQ-STC that can be
controlled by an external source. These timing signals can also be
controlled by signals generated internally to the DAQ-STC, and these
selections are fully software-configurable. Figure 3-3 shows an example of
the signal routing multiplexer controlling the CONVERT* signal.
PCI.book Page 6 Wednesday, September 16, 1998 9:09 AM
