National Instruments DAQ PCI-6023E Programmer'S Manual Download | Manualshive

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National Instruments Corporation

2-1

PCI E Series RLPM

2

Theory of Operation

This chapter contains a functional overview of the PCI E Series boards and
explains the operation of each functional unit making up the PCI E Series
boards.

Functional Overview

The block diagram in Figures 2-1 through 2-5 give a functional overview
of each PCI E Series board.

Figure 2-1.

PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram

Timing

PFI / Trigger

I/O Connector

3

2

2

RTSI Bus

Digital I/O (8)

12-Bit

Sampling

A/D

Converter

Configuration

Memory

REF

Buffer

+

Programmable
Gain
Amplifier
–

Calibration

Mux

Mux Mode
Selection
Switches

Analog

Muxes

Voltage

REF

Calibration

DACs

4

Calibration

DACs

DAC0

DAC1

DAQ - STC

Analog Input

Timing/Control

Analog Output
Timing/Control

Digital I/O

Trigger

Counter/

Timing I/O

RTSI Bus

Interface

DMA/

Interrupt
Request

Bus

Interface

(8)*

(8)*

AI Control

IRQ

DMA

AO Control

DAC

FIFO

Data (16)

Trigger Level

DACs

Analog
Trigger

Circuitry

Data (16)

ADC

FIFO

Trigger

PCI Bus

EEPROM

Address/Data

Control

Data (16)

Analog

Input

Control

EEPROM

Control

DMA

Interface

MIO

Interface

DAQ-STC

Bus

Interface

Analog
Output
Control

I/O

Bus

Interface

MINI

MITE

Generic

Bus

Interface

PCI
Bus

Interface

Address (5)

*(32) for the PCI-6071E

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Summary of Contents for DAQ PCI-6023E

Page 1: ...DAQ PCI E Series Register Level Programmer Manual Multifunction I O Boards for PCI Bus Computers PCI E Series RLPM November 1998 Edition Part Number 341079B 01 ...

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Page 3: ...OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in perf...

Page 4: ...log Input Circuitry 2 8 Data Acquisition Timing Circuitry 2 11 Single Read Timing 2 11 Data Acquisition Sequence Timing 2 12 Posttrigger and Pretrigger Acquisition 2 18 Analog Triggering 2 19 Analog Output and Timing Circuitry 2 20 Analog Output Circuitry 2 21 Analog Output Timing Circuitry 2 22 Single Point Output 2 22 Waveform Generation 2 23 Digital I O Circuitry 2 24 Timing I O Circuitry 2 24 ...

Page 5: ...G0 G1 Select Register 3 23 DAQ STC Register Group 3 24 FIFO Strobe Register Group 3 24 Configuration Memory Clear Register 3 24 ADC FIFO Clear Register 3 24 DAC FIFO Clear Register 3 24 Chapter 4 Programming PCl Local Bus 4 1 PCI Initialization for the IBM Compatible System 4 2 Re mapping the PCI E Series Board 4 3 PCI Initialization for the Macintosh 4 4 Windowing Registers 4 5 Programming Exampl...

Page 6: ...rpose Counter Timer 4 45 Example 1 4 45 Example 2 4 47 Example 3 4 49 RTSI Trigger Lines Programming Considerations 4 52 Analog Triggering 4 52 Interrupt Programming 4 56 Interrupt Sharing 4 56 DMA Programming 4 57 The Link Chaining Mode for DMA Transfer 4 58 Chapter 5 Calibration About the EEPROM 5 1 Calibration DACs 5 14 NI DAQ Calibration Function 5 17 Appendix A Customer Communication Glossary...

Page 7: ...g Rate 2 16 Figure 2 14 Multirate Scanning without Ghost 2 17 Figure 2 15 Occurrences of Conversion on Channel 1 in Example 3 2 17 Figure 2 16 Successive Scans Using Ghost 2 17 Figure 2 17 Analog Output Circuitry Block Diagram 2 20 Figure 2 18 DAQ STC Counter Diagram 2 24 Figure 2 19 RTSI Bus Interface Circuitry Block Diagram 2 26 Figure 4 1 Analog Trigger Structure 4 54 Figure 4 2 DMA Structure 4...

Page 8: ...CI 6071E EEPROM Map 5 3 Table 5 2 PCI MIO 16XE 50 EEPROM Map 5 5 Table 5 3 PCI MIO 16XE 10 PCI 6031E PCI 6032E and PCI 6033E EEPROM Map 5 7 Table 5 4 PCI 6023E EEPROM Map 5 9 Table 5 5 PCI 6024E and PCI 6025E EEPROM Map 5 10 Table 5 6 PCI 6052E EEPROM Map 5 12 Table 5 7 Type of CALDAC Used on Board 5 14 ...

Page 9: ... DAQ STC Technical Reference Manual You must use your register level programmer manual along with the DAQ STC Technical Reference Manual for a complete understanding of PCI E Series board programming Unless otherwise noted text applies to all boards in the PCI E Series The PCI E Series boards are PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 PCI MIO 16XE 50 PCI 6023E PCI 6024E PCI 6025E PCI 6031E MI...

Page 10: ...ow to calibrate the analog input and output sections of the PCI E Series boards by reading calibration constants from the EEPROM and writing them to the calibration DACs Appendix A Customer Communication contains forms you can use to request help from National Instruments or to comment on our products and manuals The Glossary contains an alphabetical list and description of terms used in this manu...

Page 11: ...is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from programs PC PC refers to the IBM PC AT and compatible computers with the PCI bus Related Documentation The following National Instruments manuals contain general information and operating ...

Page 12: ...Note Revision C and earlier versions of the PCI MIO 16XE 50 use the MITE as the interface chip and do not support the DMA feature The PCI E Series boards use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total ...

Page 13: ...ation generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ boards Your PCI E Series board is completely software configurable Refer to your PCI E Series User Manual if you have not already installed and configured your board ...

Page 14: ...rter Configuration Memory REF Buffer Programmable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 AI Control IRQ DMA AO Control DAC FIFO Data 16 Trigger Le...

Page 15: ...Calibration DACs DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 AI Control IRQ DMA AO Control DAC FIFO Data 16 Trigger Level DACs Analog Trigger Circuitry Data 16 ADC FIFO Trigger PCI Bus EEPROM Address Data Control Data 16 Analog Input Control EEPROM Control DMA Interface ...

Page 16: ...REF Calibration DACs Dither Generator Calibration DACs 82C55A DAC0 DAC1 NOT ON 6023E Analog Output DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Interface Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 AI Control Address Data Control Data Analog Input Control EEPROM Control DMA Interface DAQ APE DAQ STC Bus Interface I O Bus Int...

Page 17: ...Interface PCI Bus Interface Address 5 Timing PFI Trigger I O Connector 3 RTSI Bus Digital I O 8 16 Bit Sampling A D Converter Configuration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Trigger Analog Trigger Circuitry 2 Trigger Level DACs DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Count...

Page 18: ...manual is skeletal in nature and is sufficient in most cases For register level programming information refer to the DAQ STC Technical Reference Manual Timing PFI Trigger I O Connector 2 2 RTSI Bus PCI Bus Digital I O 8 16 Bit Sampling A D Converter Configuration Memory Programmable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration D...

Page 19: ...ds use only 8 bit or 16 bit transfers The bus mastering capabilities of the MITE provides high speed data transfer between the board and system memory The MITE contains three DMA channels that can be used simultaneously for data transfer with analog input analog output and the general purpose counters The MITE can control the PCI bus and transfer the data without interrupting the host processor Th...

Page 20: ...cuitry The PCI E Series boards have 16 and 64 analog input channels and a timing core within the DAQ STC that is dedicated to analog input operation Figure 2 7 shows a general block diagram for the analog input circuitry PCI Bus DAQ STC MITE PCI Interface Chip INTA System Arbitration Interface Control Data Address Address Data Control Interrupt Control Data IRQOUT0 ...

Page 21: ...s to use for each conversion Each entry in the configuration memory includes channel type channel number bank gain polarity dither general trigger and last channel The configuration memory is a 512 entry deep FIFO that is initialized prior to the start of the acquisition sequence It can be incremented after every conversion allowing the analog input configuration to vary on a per conversion basis ...

Page 22: ...ion while the bank field indicates which bank of 16 channels is active This bank field is used on boards that have more than 16 channels These bits control the input multiplexers The programmable gain instrumentation amplifier PGIA serves two purposes on the PCI E Series boards The PGIA applies gain to the input signal amplifying an analog input signal before sampling and conversion to increase me...

Page 23: ...E Series boards use sampling successive approximation ADCs with 12 or 16 bits of resolution with maximum conversion rates between 50 µs and 800 ns The converter can resolve its input range into 4 096 different steps for the 12 bit ADC and 65 536 for the 16 bit ADC The input range of the 12 bit boards is 5 V in bipolar mode and 0 to 10 V in unipolar mode These modes correspond to ranges of 2 048 to...

Page 24: ...just input offset output offset and gain errors associated with the analog input section When the board leaves the factory the upper one fourth of the EEPROM is protected and cannot be overwritten The lower three fourths is unprotected and the top fourth of that can be used to store alternate calibration constants for the different conditions under which you use the board Data Acquisition Timing C...

Page 25: ... gating you must program the boards to automatically generate timed signals that initiate and gate conversions This is known as a data acquisition DAQ sequence Data Acquisition Sequence Timing The following counters are used for a data acquisition sequence Scan interval SI 24 bits Sample interval SI2 16 bits Divide by DIV 16 bits Scan counter SC 24 bits This section presents a concise summary of o...

Page 26: ...configuration memory advances by one and selects the next set of analog input conditions channel number gain polarity etc A STOP pulse ends the SCAN sequence This STOP could be generated in two ways either by using the LASTCHANNEL bit in the configuration memory or by programming the 16 bit DIV counter to count the number of conversions per SCAN and using the terminal count of the DIV counter as a...

Page 27: ...ends the scan Example 1 allows you to sample all three channels at a rate of 10 kS s per channel 100 µs sample interval period To achieve different rates for different channels you must do multirate scanning Multirate Scanning without Using Ghost Example 2 To sample channel 0 at 10 kS s and channel 1 at 5 kS s both at gain 1 with 50 scans program the configuration memory as follows 1 Channel 0 gai...

Page 28: ...io of sampling rates The effective scan interval of the slower channel will be at the rate of the faster channel This implementation requires x scan sequences in the configuration memory Also you can implement a 1 1 x or 1 x mx ratio for three channels where m is a non negative integer Figures 2 11 2 12 and 2 13 show timing sequences for different ratios In these figures the numbers above the CONV...

Page 29: ...s but the data is not stored in the analog input FIFO In other words a conversion is performed and the data is thrown away By using this option multirate scanning with ratios such as x y are possible within the limits imposed by the size of the configuration memory Figures 2 14 and 2 16 illustrate the advantages of using the ghost feature Figure 2 15 shows Example 3 timing and Figure 2 16 shows th...

Page 30: ...ive occurrences of convert pulses in Figure 2 14 Figure 2 15 Occurrences of Conversion on Channel 1 in Example 3 To rectify the problem use ghost as illustrated in Figure 2 16 Figure 2 16 Successive Scans Using Ghost The shaded conversions are ghost conversions The short arrows indicate channel 0 samples and the long arrows indicate channel 1 samples that are actually stored in the FIFOs 0 0 0 1 1...

Page 31: ...used as a trigger line in the posttrigger mode Since the START1 pulse can be generated through software by strobing a bit all of the examples discussed so far can be generally categorized as posttrigger acquisition In the classic posttrigger mode case the data acquisition circuitry is armed by software but does not start acquiring data until a pulse is given on the START1 line Then the acquisition...

Page 32: ...llows continuous software initiated acquisition to continue indefinitely In this mode the SC gets reloaded each time it counts down to zero The acquisition can be stopped by disarming the SC When the SC counts down to zero acquisition stops Analog Triggering All PCI E Series boards except the PCI MIO 16XE 50 PCI 6023E PCI 6024E and PCI 6025E have an analog trigger in addition to the digital trigge...

Page 33: ...sed here refer to the DAQ STC Technical Reference Manual Analog Output and Timing Circuitry The PCI E Series boards except the PCI 6023E PCI 6032E and PCI 6033E have two analog output channels and a timing core within the DAQ STC that is dedicated to analog output operation Figure 2 17 shows a general block diagram for the analog output circuitry Figure 2 17 Analog Output Circuitry Block Diagram D...

Page 34: ...C signal If you apply an AC reference the analog output channel acts as a signal attenuator and the AC signal appears at the output attenuated by the digital code For unipolar output the voltage is simply attenuated Four quadrant multiplication occurs in bipolar output where the signal will not only be attenuated but also inverted for negative digital codes The DAC output can be configured to prod...

Page 35: ...tput repetitively without any further data transfer to the FIFO The PCI MIO 16XE 50 PCI 6024E and PCI 6025E has a zero depth virtual FIFO Analog Output Timing Circuitry This section describes the different methods of setting the analog output voltage including single point updating and waveform generation The DAQ STC provides the timing signals necessary to write to the DACs and update them The DA...

Page 36: ...pulse This data transfer will be from the analog output FIFO Some of the boards have large 2 kword FIFOs and some have 512 word FIFOs others are zero deep virtual FIFOs The large FIFOs are true FIFOs where data can be written to the FIFOs as long as they are not full and can be read from when they are not empty In this case the DAQ STC will transfer the data from the FIFO to the DACs when the FIFO...

Page 37: ...is used as the serial data in pin and DIO0 is used as the serial data out pin You can use handshaking with the EXTSTROBE pin to do either parallel or serial data transfer Refer to the DAQ STC Technical Reference Manual for more details on the DIO features The external strobe signal EXTSTROBE is a general purpose strobe signal Software can set the output of the EXTSTROBE pin to either a high or low...

Page 38: ...t tri state the corresponding DIO line The SOURCE of these counters can be selected to be one of the 10 PFI lines the seven RTSI lines the internal 20 MHz or 100 kHz timebases or the TC of the other counter With the last option the two counters can be concatenated Similarly the GATE can also be selected from a variety of different sources The sources for both of these signals are described in the ...

Page 39: ...bus signals can be driven by eight internally generated timing signals and the four RTSI board signals Similarly the four RTSI board signals can be driven by any of the RTSI trigger bus signals Of the four RTSI board signals only one is used By programming certain bits in the DAQ STC you can drive the CONVERT pulse onto RTSI_BRD0 and then onto any of the TRIGGER lines RTSI Bus Connector DAQ STC TR...

Page 40: ...ress of the PCI E Series board Registers are grouped in the table by function Each register group is introduced in the order shown in Table 3 1 then described in detail including a bit by bit description The DAQ STC has 180 different registers The more frequently used registers have been given lower offset addresses and are shown in Table 3 1 as the DAQ STC Register Group The advantage of having l...

Page 41: ...on DAC FIFO Data DAC0 Direct Data DAC1 Direct Data 16 1E 18 1A 22 30 24 26 Write only Write only Write only Write only 16 bit 16 bit 16 bit 16 bit DMA Control Register Group AI AO Select G0 G1 Select 09 0B 9 11 Write only Write only 8 bit 8 bit DAQ STC Register Group Window Address Window Data Interrupt A Acknowledge Interrupt B Acknowledge AI Command 2 AO Command 2 G0 Command G1 Command AI Status...

Page 42: ...e and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB shown on the left bit 15 for a 16 bit register bit 7 for an 8 bit register and the LSB shown on the right bit 0 A square represents each bit and contains the bit name An asterisk after the bit name indicates that the bit is inverted negative logic In many of the reg...

Page 43: ... data previously shifted into the DACs 3 SerDacLd0 Serial DAC Load0 This bit is used to load the first set of serial DACs with the serial data previously shifted into the DACs 2 EEPromCS EEPROM Chip Select This bit controls the chip select of the onboard EEPROM used to store calibration constants When EEPromCS is set the chip select signal to the EEPROM is enabled 1 SerData Serial Data This bit is...

Page 44: ... Address Base address 0F hex Type Write only Word Size 8 bit Bit Map Bit Name Description 7 Int Ext Trig Internal External Analog Trigger This bit controls the analog trigger source If this bit is set the output of the PGIA2 is selected as the trigger source If this bit is cleared the TRIG1 signal from the I O connector is selected as the trigger source 6 0 Reserved Reserved Always write 0 to thes...

Page 45: ...the status of the calibration EEPROM output Address Base address 01 hex Type Read only Word Size 8 bit Bit Map Bit Name Description 7 1 Reserved Reserved Ignore returned bits 0 PROMOUT EEPROM Output Data This bit reflects the serial output data of the serial EEPROM 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved PROMOUT ...

Page 46: ...e used to read the ADC FIFO contents Reading the ADC FIFO Data Register location transfers data from the PCI E Series ADC data FIFO to the computer Writing to the Configuration Memory Low and Configuration Memory High Register locations sets up channel configuration information for the analog input section This information is necessary for single conversions as well as for single and multiple chan...

Page 47: ...ble in two different binary formats straight binary which generates only positive numbers or two s complement binary which generates both positive and negative numbers The binary format used is determined by the mode in which the ADC is configured Following is the bit pattern returned for either format Address Base address 1C hex Type Read only Word Size 16 bit Bit Map Bit Name Description 15 0 D ...

Page 48: ...e than one occurrence of the LastChan bit is possible in the configuration memory list for the interval scanning mode For example there can be multiple scan sequences in one memory list 14 13 Reserved Reserved Always write 0 to these bits 11 10 7 3 12 GenTrig General Trigger This bit synchronizes actions in the DAQ STC with the scan list When this bit is set an active low trigger pulse is sent int...

Page 49: ...re in straight binary format When Unip Bip is clear the ADC is configured for bipolar operation and values The data values are two s complement and automatically sign extended 2 0 Gain 2 0 Channel Gain Select 2 through 0 These three bits control the gain settings of the input PGIA for the selected analog channel The gains shown in Table 3 3 can be selected on the PCI E Series boards Table 3 3 PGIA...

Page 50: ... Address Base address 12 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 Reserved Reserved Always write 0 to these bits 11 6 14 12 ChanType 2 0 Channel Type 2 through 0 These bits indicate which type of resource is active for the current entry in the scan list The following table lists the valid channel types 15 14 13 12 11 10 9 8 Reserved ChanType2 ChanType1 ChanType0 Reserve...

Page 51: ...Channel Select 3 through 0 These bits indicate which channel is active for the current resource in the scan list Not every resource uses all 16 channels in a bank Channel assignments for all PCI E Series or higher boards follow Table 3 4 Calibration Channel Assignments Chan Type 2 0 CAL Chan 3 0 PGIA PGIA Purpose 0000 AOGND1 AOGND1 ADC Offset 0001 AOGND AIGND Ground Differential 00102 DAC0OUT AOGN...

Page 52: ...Ch10 0011 ACh3 ACh11 0100 ACh4 ACh12 0001 ACh5 ACh13 0110 ACh6 ACh14 0111 ACh7 ACh15 1xxx Reserved Reserved Table 3 6 Nonreferenced Single Ended Channel Assignments Chan Type 2 0 NRSE Chan 3 0 PGIA PGIA 0000 ACh0 AISense 0001 ACh1 AISense 0010 ACh2 AISense 0011 ACh3 AISense 0100 ACh4 AISense 0101 ACh5 AISense 0110 ACh6 AISense 0111 ACh7 AISense 1000 ACh8 AISense 1001 ACh9 AISense 1010 ACh10 AISens...

Page 53: ...0 RSE Chan 3 0 PGIA PGIA 0000 ACh0 AIGround 0001 ACh1 AIGround 0010 ACh2 AIGround 0011 ACh3 AIGround 0100 ACh4 AIGround 0101 ACh5 AIGround 0110 ACh6 AIGround 0111 ACh7 AIGround 1000 ACh8 AIGround 1001 ACh9 AIGround 1010 ACh10 AIGround 1011 ACh11 AIGround 1100 ACh12 AIGround 1001 ACh13 AIGround 1110 ACh14 AIGround 1111 ACh15 AIGround Table 3 6 Nonreferenced Single Ended Channel Assignments Continue...

Page 54: ...nsferred to the DACs in one of two ways Data can be directly sent to the DACs from the host computer or buffered from the host by the DAC data FIFO Table 3 8 Auxiliary Channel Assignments Chan Type 2 0 AUX Chan 3 0 PGIA PGIA Purpose 0100 TEMP AIGND Onboard temperature sensor 100 mV 40 C 1 75 V 125 C 0000 0011 0101 1111 Reserved Reserved The temperature sensor is not supported on Revision D and ear...

Page 55: ...t connects the reference for both DACs to ground when this bit is set This is useful for calibration of the DAC linearity This bit is not currently implemented as a separate selection for the two DACs Therefore its state is determined by the last value written to this bit field This bit is reserved on the PCI MIO 16XE 50 PCI MIO 16XE 10 and PCI 6031E It should be set to 0 2 ExtRef External Referen...

Page 56: ... 6032E and PCI 6031E It should be set to 0 0 BipDac Bipolar DAC This bit configures the voltage range of the selected DAC If this bit is set then the DAC is configured for bipolar operation of Vref to Vref In this mode data written to the DAC is interpreted in two s complement format If this bit is cleared then the DAC is configured for unipolar operation of 0 V to Vref In this mode data written t...

Page 57: ...e full flag is available on the boards with the 0 word deep DAC data virtual FIFO Whenever the FIFO is not full the host is free to write additional data Address Base address 1E hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 0 D 15 0 Data bits 15 through 0 The data to be written to the DAC data FIFO This data is interpreted in straight binary form when DAC is configured for u...

Page 58: ... 15 through 0 The data to be written directly to DAC0 This data is interpreted in straight binary form when DAC0 is configured for unipolar operation In unipolar mode the valid range is 0 to 65 536 for a 16 bit DAC and 0 to 4 096 for a 12 bit DAC When DAC0 is configured for bipolar operation the data is interpreted in two s complement form In bipolar mode the valid range is 32 768 to 32 767 for a ...

Page 59: ... 15 through 0 The data to be written directly to DAC1 This data is interpreted in straight binary form when DAC1 is configured for unipolar operation In unipolar mode the valid range is 0 to 65 536 for a 16 bit DAC and 0 to 4 096 for a 12 bit DAC When DAC1 is configured for bipolar operation the data is interpreted in two s complement form In bipolar mode the valid range is 32 768 to 32 767 for a ...

Page 60: ... the PCI E Series boards DMA interface The AI AO Select and G0 G1 Select Registers select the DMA channels for the analog input analog output and general purpose counter timer resources The PCI E Series boards support four logical channels which are routed through the three physical DMA channels of the MITE Only one physical DMA channel is supported on the PCI 6023E PCI 6024E and PCI 6025E ...

Page 61: ...ription 7 4 Reserved Reserved Always write 0 to these bits for PCI 6032E and PCI 6033E only 7 4 Output D A Analog Output Logical Channel D through A These four bits select the logical channels of the MITE to be used by the analog output You can only set one of these bits at a time except for the PCI 6032E and PCI 6033E 3 0 Input D A Analog Input Logical Channel D through A These four bits select t...

Page 62: ...ess Base address 0B hex Type Write only Word Size 8 bit Bit Map Bit Name Description 7 4 GPCT1 D A General Purpose Counter Timer 1 Logical Channel C through A These four bits select the MITE logical channels that the GPCT1 uses You can only set one of these bits at a time 3 0 GPCT0 D A General Purpose Counter Timer 0 Logical Channel C through A These four bits select the MITE logical channels that...

Page 63: ...tion Memory Clear Register clears all information in the channel configuration memory and resets the write pointer to the first location in the memory Window Address 52 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used ADC FIFO Clear Register Accessing the ADC FIFO Clear Register clears all information in the ADC data FIFO Window Address 53 hex Type Write only Word Size 16 b...

Page 64: ...programming style becomes very modular and a functional description of every programming step is easily understood Because the DAQ STC Technical Reference Manual has detailed step by step programming instructions this register level programmer manual gives a series of common programming examples with references to the DAQ STC Technical Reference Manual The program for each example is presented as ...

Page 65: ...rd to operate properly this chip must be configured Ordinarily NI DAQ performs this function but if you are not using NI DAQ then you must configure the MITE ASIC chip The following sections explain how to accomplish this The initialization is done by the Setup_Mite function found on the companion diskette Setup_Mite performs the following functions 1 It detects whether the PCI bus is present usin...

Page 66: ...le The pseudo code shown below demonstrates how to re map the board below 1 MB If you do not want to re map the board you must still perform steps 4 and 5 to enable the device window of the MITE All values and bit masks are 32 bits and all pseudo code functions are of the format function_name address data This example assumes the new BAR0 address is 0xd000 and BAR1 address is 0xd1000 If you are us...

Page 67: ...are not using NI DAQ then you must configure the MITE ASIC chip The following sections explain how to accomplish this The initialization is done by the Setup_Mite function Setup_Mite consists of two parts First the PCI bus is scanned for all National instruments PCI E Series boards An NI DAQ function1 finds all PCI boards that contain the National Instruments vendor ID 0x1093 and PCI E Series boar...

Page 68: ...indowed mode write the address offset to the Window_Address_Register read from the Window_Data_Read_Register Programming Examples The programs presented in this chapter are broken into three sections Digital I O Analog Input and Analog Output Each example provides the pseudo code for the main program The examples follow the procedure presented in detail in the DAQ STC Technical Reference Manual an...

Page 69: ... Board_Write Board_Write_8bit and Board_Read In addition Macintosh users should include the NI DAQ library since the NI DAQ library has the low level routines for reading the configuration Before beginning register level programming of the analog input and analog output sections you should test the Windowed addressing scheme To test the Windowed addressing scheme use a simple example to operate on...

Page 70: ... 7 of the DAQ STC Technical Reference Manual 1 Set up the PCI board resources Use the function Setup_Mite provided on the Companion Disk 2 Configure all the digital lines as outputs DIO_Control_Register 0xFF 3 Output the digital patterns for i 0 i 255 i DIO_Output_Register i Example 2 This example shows how to perform digital I O Configure digital lines 0 2 4 and 6 as outputs and the remaining lin...

Page 71: ... board registers and DAQ STC registers The following functions configure the board by calling the Board_Read and Board_Write functions Setup_Mite Configure_Board Analog input DAQ STC programming consists of the following functions which call the DAQ_STC_Windowed_Mode_Read and DAQ_STC_Windowed_Mode_Write functions AI_Initialize_Configuration_Memory_Ouput MSC_Clock_Configure Clear_FIFO AI_Reset_All ...

Page 72: ...lue to the input voltage The first two steps set up the E Series board and the subsequent steps configure the DAQ STC 1 Set up the PCI board resources Use the function Setup_Mite provided on the Companion Disk 2 Configure the analog channel for the given settings The function Configure_Board clears the configuration memory clears the ADC FIFO and then sets channel 0 to the given settings Clearing ...

Page 73: ...start 1 Interrupt_A_Ack_Register 0x3F80 AI_Mode_1_Register Reserved one 1 AI start stop 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 6 AI_Board_Personalize sets the DAQ STC for the PCI E Series board Joint_Reset_Register AI configuration start 1 Clock_and_FOUT_Register Output divide by two 1 Set the AI_Personal_Register 0xA4A0 Set the AI_Output_Control Register 0x032E Joi...

Page 74: ... 1 AI_Mode_1_Register Trigger once 1 AI_Trigger_Select_Register Start edge 1 Start sync 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 10 The function AI_Scan_Start selects the scan start event Joint_Reset_Register AI configuration start 1 AI_Start_Stop_Select_Register Start edge 1 Start sync 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 11 Call the...

Page 75: ...scan interval of 1 ms The scan list contains channels 5 4 1 and 0 respectively The channels are configured as RSE at a gain of 1 Within each scan the sample interval should be 100 µs Dithering should remain off during the operation No external multiplexers are used Use polled input to acquire the data 1 Perform Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel ...

Page 76: ...ry ticks 1 19999 Joint_Reset_Register AI configuration start 0 AI configuration end 1 6 Perform Analog Input Example 1 Step 11 7 Convert_Signal selects the convert signal for the acquisition Joint_Reset_Register AI configuration start 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 1999 AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 1999 AI_Mode_2_Register AI SI2 reload mode 1 AI_Command_1_Registe...

Page 77: ... of 1 Within each scan the sample interval should be 100 µs Dithering should remain off during the operation No external multiplexers are used Use interrupts to acquire the data Only minor modifications to Analog Input Example 2 are needed for this example Instead of installing the interrupt service routine ISR as an interrupt this example emulates the operation of the interrupt by polling the sta...

Page 78: ...the number of scans Joint_Reset_Register AI configuration start 1 AI_SC_Load_A_Registers 24 bits Number of posttrigger scans 1 4 AI_Command_1_Register AI SC Load 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 5 The function AI_Scan_Start selects the scan start event Joint_Reset_Register AI configuration start 1 AI_Start_Stop_Select_Register Start edge 1 Start sync 1 AI_SI_L...

Page 79: ...itial load source 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 8 Perform Analog Input Example 1 Step 4 9 The function AI_Interrupt_Enable enables interrupts for the acquisition Interrupt_A_Enable_Register AI FIFO interrupt enable 1 AI error interrupt enable 1 Interrupt_Control_Register MSC IRQ pin 0 MSC IRQ enable 1 10 Call AI_Arming to arm the analog input counter AI_Com...

Page 80: ...s example constructs a linked list to contain the information about the buffers such as their physical address logical address and total transfer bytes You need to pass the linked list head node to MITE_DMAProgram to program the MITE Since the physical address calculation is only valid for real mode on a PC this example only runs under DOS If you want to program DMA under other operating systems y...

Page 81: ...er AI configuration start 1 AI_Start_Stop_Select_Register Start edge 1 Start sync 1 AI_SI_Load_A_Registers 24 bits AI SI special ticks 1 1 AI_Command_1_Register AI SI load 1 AI_SI_Load_A_Registers 24 bits AI SI ordinary ticks 1 19999 Joint_Reset_Register AI configuration start 0 AI configuration end 1 6 Perform Analog Input Example 1 Step 11 7 Convert_Signal selects the convert signal for the acqu...

Page 82: ...cal address and logical address and total transfer bytes for that buffer 11 Set up the DRQ channel AI_AO_Select_Register DMA Channel A enable 1 12 Call the function MITE_DMAProgram to set up the MITE for DMA transfer You need to pass the following parameters to the function BufferinfoNodeHeadPtr Point to the buffer information linked list head node NumberOfBuffer Number of buffers you use for DMA ...

Page 83: ...onstruct the output buffer information linked list Then perform all the steps above but pass OUTPUT for the direction parameter to the function MITE_DMAProgram To perform two or more DMA transfers at the same time use different DMA and DRQ channels for different DMA transfers For example you want to have DMA transfers for analog input and analog output at the same time Use DRQ channel 0 and DMA ch...

Page 84: ... Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel in the scan list Only channel 0 has Last channel set to 1 3 Perform Analog Input Example 1 Steps 3 through 8 4 Call AI_Trigger_Signals to set the triggering options Joint_Reset_Register AI configuration start 1 AI_Mode_1_Register AI trigger once 1 AI_Trigger_Select_Register 0x8061 Joint_Reset_Register AI config...

Page 85: ...AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 1999 AI_Mode_2_Register AI SI2 reload mode 1 AI_Command_1_Register AI SI2 load 1 AI_Mode_2_Register AI SI2 initial load source 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 9 Perform Analog Input Example 1 Step 4 10 Call AI_Arming to arm the analog input counter AI_Command_1_Register AI SC arm 1 AI SI arm 0 AI SI2 arm 1 AI DIV...

Page 86: ...ple 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel in the scan list Only channel 0 has Last channel set to 1 3 Perform Analog Input Example 1 Steps 3 through 8 4 Call AI_Trigger_Signals to set the triggering options Joint_Reset_Register AI configuration start 1 AI_Mode_1_Register AI trigger once 1 AI_Trigger_Select_Register 0xB161 Joint_Reset_Register AI configuration start 0 AI...

Page 87: ...ters 24 bits AI SI ordinary ticks 1 19999 Joint_Reset_Register AI configuration start 0 AI configuration end 1 7 Perform Analog Input Example 1 Step 11 8 Convert_Signal selects the convert signal for the acquisition Joint_Reset_Register AI configuration start 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 1999 AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 1999 AI_Mode_2_Register AI SI2 reload mo...

Page 88: ... as Example 2 but as a single wire acquisition Acquire 5 scans The scan list contains channels 5 4 1 and 0 respectively each at a gain of 1 and in RSE mode The START and CONVERT signals should be applied to PFI0 Use polled input to read the AI FIFO data 1 Perform Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for each channel in the scan list Only channel 0 has Last channel ...

Page 89: ... enable 1 AI START STOP gate enable 1 AI_Mode_1_Register AI CONVERT source select 1 AI CONVERT source polarity 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 8 Perform Analog Input Example 1 Step 4 9 Call AI_Arming to arm the analog input counter AI_Command_1_Register AI SC arm 1 AI SI arm 0 AI SI2 arm 0 AI DIV arm 1 10 The function AI_Start_The_Acquisition starts the acqui...

Page 90: ...hrough 6 4 Call the function AI_Initialize_Configuration_Memory_Output to output one pulse and access the first value in the configuration FIFO This function also configures the DIO circuitry for the AMUX 64T AI_Command_1_Register AI convert pulse 1 DIO_Control_Register 0x0003 DIO_Output_Register 0x0003 DIO_Control_Register 0x0803 DIO_Control_Register 0x0003 5 Perform Analog Input Example 1 Steps ...

Page 91: ...n Joint_Reset_Register AI configuration start 1 AI_SI2_Load_A_Register AI SI2 special ticks 1 1 AI_SI2_Load_B_Register AI SI2 ordinary ticks 1 1 AI_Mode_2_Register AI SI2 reload mode 1 AI_Command_1_Register AI SI2 load 1 AI_Mode_2_Register AI SI2 initial load source 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 10 Perform Analog Input Example 1 Step 4 11 Call AI_Arming to ...

Page 92: ...gh 7 Compare the unscaled results to the applied voltage Read the samples using polled input 1 Perform Analog Input Example 1 Step 1 2 Perform Analog Input Example 1 Step 2 for channels 0 and 1 Only channel 1 has Last channel set to 1 3 Perform Analog Input Example 1 Steps 3 through 6 4 Call the function AI_Initialize_Configuration_Memory_Output to output one pulse and access the first value in th...

Page 93: ...umber of scans Joint_Reset_Register AI configuration start 1 AI_SC_Load_A_Registers 24 bits Number of posttrigger scans 1 99 AI_Command_1_Register AI SC Load 1 Joint_Reset_Register AI configuration start 0 AI configuration end 1 8 The function AI_Scan_Start selects the scan start event Joint_Reset_Register AI configuration start 1 AI_START_STOP_Select_Register 0x0060 AI_SI_Load_A_Registers 24 bits...

Page 94: ...t 0 AI configuration end 1 11 Perform Analog Input Example 1 Step 4 12 Call AI_Arming to arm the analog input counter AI_Command_1_Register AI SC arm 1 AI SI arm 1 AI SI2 arm 1 AI DIV arm 1 13 Now start the acquisition with AI_Start_The_Acquisition AI_Command_2_Register AI START1 pulse 1 14 Poll the AI FIFO not empty flag in the AI_Status_1_Register until not empty and read the ADC FIFO data in th...

Page 95: ...e in complexity more of these functions will be necessary The functions will be presented in the applicable examples subsequent examples address only the specific differences from Example 1 This manual provides the structure and pseudo code for each example The PCI E Series Register Level Programmer Manual Companion Disk contains the complete programs The following pseudo code examples and the pro...

Page 96: ...F98 Joint_Reset_Register AO configuration start 0 AO configuration end 1 4 Call AO_Board_Personalize to configure the DAQ STC Joint_Reset_Register AO_Configuration_Start 1 If Board Type PCI MIO 16E 1 PCI 6071E or PCI MIO 16E 4 AO_Personal_Register 0x1410 Else AO_Personal_Register 0x1430 Clock_and_FOUT_Register 0x1B20 AO_Output_Control_Register 0x0000 AO_START_Select_Register 0x 0000 Joint_Reset_Re...

Page 97: ...tialize the buffer with 3000 points Use polled writes to write each point to the data FIFO Updates occur every 2 ms Output the buffer five times Confirm operation with an oscilloscope 1 Perform Analog Output Example 1 Step 1 2 Load an array with the voltages of the waveform to be output In bipolar mode 10 V corresponds to 2 047 0x07FF and 10 V corresponds to 2 048 0xF800 To convert the voltage you...

Page 98: ...configuration end 1 8 Call AO_Board_Personalize to configure the DAQ STC for the MIO board Use the following bitfield settings Joint_Reset_Register AO_Configuration_Start 1 If Board Type PCI MIO 16E 1 PCI 6071E or PCI MIO 16E 4 AO_Personal_Register 0x1410 Else AO_Personal_Register 0x1430 Clock_and_FOUT_Register 0x1B20 AO_Output_Control_Register 0x0000 AO_START_Select_Register 0x 0000 Joint_Reset_R...

Page 99: ...the first buffer contains 3000 points Write 2999 to UC Load Register A each subsequent buffer contains 3000 points Joint_Reset_Register AO configuration start 1 AO_Mode_1_Register AO continuous 0 AO_Mode_2_Register AO BC initial load source 0 AO_BC_Load_A_Registers 24 bits Number of buffers 1 4 AO_Command_1_Register AO BC load 1 AO_Mode_2_Register AO UC initial load source 0 AO_UC_Load_A_Registers...

Page 100: ...UI source select 0 AO UI source polarity 0 AO_Mode_2_Register AO UI initial load source 0 AO UI reload mode 0 AO_UI_Load_A_Registers 24 bits AO UI special ticks 1 1 AO_Command_1_Register AO UI load 1 AO_UI_Load_A_Registers 24 bits AO UI ordinary ticks 1 9C40 Joint_Reset_Register AO configuration start 0 AO configuration end 1 12 Call AO_Channels to select single channel output Joint_Reset_Register...

Page 101: ...e analog output to stop on overrun error Joint_Reset_Register AO configuration start 1 AO_Mode_3_Register 0x0020 Joint_Reset_Register AO configuration start 0 AO configuration end 1 15 Call AO_FIFO to disable the FIFO retransmit Joint_Reset_Register AO configuration start 1 AO_Mode_2_Register AO FIFO retransmit enable 0 Joint_Reset_Register AO configuration start 0 AO configuration end 1 16 Call K...

Page 102: ...6XE 50 boards because it has virtual analog output FIFOs Initialize the data FIFO with a 100 point buffer Output the buffer 50 times The update interval is 100 µs Confirm operation with an oscilloscope 1 Perform Analog Output Example 2 Steps 1 through 9 2 Call AO_Counting to program the buffer size and the number of buffers Configure the DAQ STC for non continuous operation AO will stop on BC_TC L...

Page 103: ...rce to AO_IN_TIMEBASE1 Load the UI counter with 1 minimum delay from the START1 to the first UPDATE Write 1999 to UI Load Register A 100 µs update interval Joint_Reset_Register AO configuration start 1 AO_Command_2_Register AO BC gate enable 0 AO_Mode_1_Register AO UPDATE source select 0 AO UPDATE source polarity 0 AO_Mode_1_Register AO UI source select 0 AO UI source polarity 0 AO_Mode_2_Register...

Page 104: ...all AO_Start_The_Acquisition to pulse the software START1 trigger AO_Command_2_Register AO START1 pulse 1 Example 4 This example generates a waveform using local buffer mode with an external UPDATE and external trigger This example does not support those boards with a virtual FIFO due to the use of the local buffer mode but the programming of the external UPDATE and START1 applies to all boards In...

Page 105: ...Load the BC counter with 49 output the buffer 50 times Load the UC counter with 100 the first buffer contains 100 points Write 99 to UC Load Register A each subsequent buffer contains 100 points Joint_Reset_Register AO configuration start 1 AO_Mode_1_Register AO continuous 0 AO_Mode_2_Register AO BC initial load source 0 AO_BC_Load_A_Registers 24 bits Number of buffers 1 49 AO_Commmand_1_Register ...

Page 106: ...tus register indicates an interrupt the main loop transfers control to the ISR To use the example ISR as an actual interrupt you need to learn how to install software interrupts on your system Generally the procedure is as follows 1 Determine the software interrupt number corresponding to the IRQ line you are using 2 Use the OS specific functions such as getvect and setvect for DOS to replace the ...

Page 107: ...er 0x554 5 Program the DAQ STC to generate interrupts on the FIFO condition Interrupt_B_Enable_Register AO FIFO interrupt enable 1 Interrupt_Control_Register Interrupt B output select IRQ number Interrupt B enable 1 6 Install the interrupt service routine to handle the interrupt service_interrupt Do If AO FIFO not full AO_DAC_FIFO_Data data increment data index counter while AO FIFO not full total...

Page 108: ...nual contains all the information on the DAQ STC general purpose counter and timer module with specific programming steps in the Programming Information section Example 1 shows simple gated event counting Example 2 shows buffered pulsewidth measurement and Example 3 provides the framework for continuous pulse generation Example 1 This is the example for gated event counting G0 counter counts the n...

Page 109: ...ter G0_Load_Source 0 G0_Load_A_Registers 24 bits G0_Load_A 0x0000 initial counter value G0_Command_Register G0_Load 1 G0_Input_Select_Register G0_Source_Select 4 PFI3 G0_Source_Polarity 0 rising edges G0_Gate_Select 5 PFI4 G0_OR_Gate 0 G0_Output_Polarity 0 active high G0_Gate_Select_Load_Source 0 G0_Mode_register G0_Output_Mode 1 one clock cycle output G0_Gate_Polarity 1 enable inversion G0_Loadin...

Page 110: ...ple 2 This is the example for buffered pulsewidth measurement The counter uses G_In_TimeBase as G_Source to measure the signal s pulsewidth on PFI4 G_Gate counting the number of edges that occur on G_Source At the completion of each pulsewidth interval for G_Gate software reads the counter values from the HW_Save_Registers An interrupt occurs after each measurement Readings are done after each gen...

Page 111: ...t_Mode 1 one clock cycle output G0_Gate_Polarity 1 enable inversion G0_Loading_On_Gate 1 G0_Loading_On_TC 0 GO_Gating_Mode 1 G0_Gate_On_Both_Edges 0 GO_Trigger_Mode_For_Edge_Gate 3 G0_Stop_Mode 0 G0_Counting_Once 0 G0_Command_Register G0_Up_Down 1 up counting G0_Bank_Switch_Enable 0 G0_Bank_Switch_Mode 0 Interrupt_A_Enable_Register G0_TC_Interrupt_Enable 0 G0_Gate_Interrupt_Enable 1 3 Call G0_Arm ...

Page 112: ...rdware saves are too fast if G0_Gate_Error_St 1 Interrupt_A_Ack_Register G0_Gate_Error_Confirm 1 if G0_TC_St 1 rollover error counter value is not correct confirm user rollover has occurred Interrupt_A_Ack_Register G0_TC_Interrupt_Ack 1 5 Call ISR in a do while loop do call Buffered_Pulse_Width_Measurement_ISR while the buffer is not done print out the buffer values Example 3 This is the example f...

Page 113: ..._Board_Divide_By_2 1 3 Call Cont_Pulse_Train_Generation to set up the DAQ STC for continuous pulse train generation Go_Mode_Register G0_Load_Source 0 G0_Load_A_Registers 24 bits G0_Load_A 0x0002 delay from the trigger 1 G0_Command_Register G0_Load 1 G0_Load_A_Registers 24 bits G0_Load_A 0x0003 pulse interval 1 G0_Load_B_Registers 24 bits G0_Load_B 0x0002 pulse width 1 G0_Mode_Register G0_Load_Sour...

Page 114: ...ulse_Train_Change G0_Bank_Switch_Mode 0 Interrupt_A_Enable_Register G0_TC_Interrupt_Enable 0 G0_Gate_Interrupt_Enable 0 4 Call G0_Out_Enable to enable GPCTR0_Out pin Analog_Trigger_Etc_Register GPFO_0_Output_Enable 1 GPFO_0_Output_Select 0 5 Call G0_Arm to begin the operation G0_Command_Register G0_Arm 1 6 Call G0_Seamless_Pulse_Train to change the pulse rate during the operation Check if you can ...

Page 115: ...he four RTSI board signals with any of the seven RTSI trigger signals and the AISTART or AISTOP signal See the DAQ STC manual for information on programming the RTSI interface The function MSC_RTSI_Pin_Configure is very straightforward and easy to use Notice that of the four RTSI board signals only RTSI_BRD0 is connected to GENTRIG0 The remaining three are unused The GENTRIG0 signal is a logical A...

Page 116: ...ig bit in the Misc Command Register controls which input is used The PGIA output is selected when this bit is set and the PFI0 TRIG1 input is selected when this bit is cleared When the PFI0 TRIG1 input is being used for an analog signal it must be disconnected from the DAQ STC PFI input You can do this by clearing the Analog_Trigger_Drive bit in the DAQ STC When the Analog_Trigger_Drive bit is set...

Page 117: ...Programming Analog Trigger section of Chapter 10 in the DAQ STC Technical Reference Manual The following example is written for the PCI MIO 16E 1 PCI MIO 16E 4 and PCI 6071 boards which use 8 bit CALDAC for the analog trigger the PCI 6052E PCI MIO 16XE 10 PCI 6031E PCI 6032E and PCI 6033E use an AD8522 which contains two 12 bit DACs The PCI MIO 16XE 50 does not support analog triggering The write ...

Page 118: ...trobe 1 1 Configuration_Memory_High_Register Channel Number 0 Channel type 3 Configuration_Memory_Low_Register Last Channel 1 Gain 1 Polarity 0 Dither enable 0 3 Perform Steps 3 through 9 of Analog Input Example 1 4 Call the function Number_of Scans to load the number of scans Joint_Reset_Register AI configuration start 1 AI_SC_Load_A_Register 24 bits Number of postrigger scan 1 99 AI_Command_1_Re...

Page 119: ...alog input interrupts general purpose Counter 0 interrupts and one pass through interrupt The Group A pass through interrupt is not used Group B handles the analog output interrupts general purpose counter 1 interrupts and one pass through interrupt The Group B pass through interrupt is not used The MSC_IRQ_Configure function found in the DAQ STC Technical Reference Manual should select the IRQ_OU...

Page 120: ...your PCI E Series board so that the analog input analog output or general purpose counter timers can generate DMA requests under appropriate circumstances There are four logical DMA channels A B C and D Each logical channel in turn can service either analog input analog output or the general purpose counter timers You must program the AO AI Select Register address 0x09 and the G0G1 Select Register...

Page 121: ... full Assert on FIFO half full and deassert on FIFO full For general purpose counter timers an interrupt is produced in buffered modes such as the buffered event counting the buffered period measurement and so on The secondary bank of interrupts in the DAQ STC is used for generating DMA requests for the general purpose counter timers The Link Chaining Mode for DMA Transfer The MITE contains DMA ch...

Page 122: ... an entry point to access the link chain After arming the DMA transfer the MITE goes through the link chain and loads the buffer s physical address into MAR Then the MITE transfers data from the FIFO to the buffers or from the buffer to the output port This process continues until the MITE reaches the empty node the node which contains all zeros Figure 4 3 illustrates the basic operation of the Li...

Page 123: ...Generating new constants results in a more accurate calibration for the actual environment in which the board is used About the EEPROM The EEPROM is used to store all non volatile information about the board including the factory and user calibration constants The PCI E Series boards use a XICOR X25040 EEPROM which is 512 by 8 bits in size and has a serial interface The signals used to interface t...

Page 124: ... to the CalDACs could result in accidental writes to the EEPROM However this is not true A write cycle to the EEPROM needs the chip select bit asserted While writing to the CalDACs make sure that this bit is cleared Clearing this bit ensures that no writes to the EEPROM occur It might also seem as though an access to the EEPROM could result in an access to the CalDACs but this is also not true The...

Page 125: ...last factory fabrication 426 Factory reference MSB 425 Factory reference LSB 424 CALDAC factory constant AI MB88341 8 bit 4 0 423 CALDAC factory constant AI MB88341 8 bit 1 0 422 CALDAC factory constant AI MB88341 8 bit 3 and 142 0 421 CALDAC factory constant AI MB88341 8 bit 2 0 420 CALDAC factory constant Bipolar AO MB88341 8 bit 5 0 419 CALDAC factory constant Bipolar AO MB88341 8 bit 7 and 132...

Page 126: ...tory constant Unipolar AO MB88341 8 bit 8 0 410 CALDAC factory constant Unipolar AO MB88341 8 bit 10 0 409 CALDAC factory constant Unipolar AO MB88341 8 bit 9 0 408 Factory calibration temperature 371 Start of the five user calibration sections 1Board Codes 205 PCI MIO 16E 1 206 PCI MIO 16E 4 207 PCI 6071E 2 Write both CALDAC addresses for these constants Table 5 1 PCI MIO 16E 1 PCI MIO 16E 4 PCI ...

Page 127: ...cation 438 Factory reference MSB 437 Factory reference LSB 436 CALDAC factory constant MSB Bipolar AI DAC8043 12 bit 1 435 CALDAC factory constant LSB Bipolar AI DAC8043 12 bit 1 434 CALDAC factory constant Bipolar AI 8800 8 bit 2 0 433 CALDAC factory constant Bipolar AI 8800 8 bit 0 0 432 CALDAC factory constant Bipolar AI 8800 8 bit 1 0 431 CALDAC factory constant MSB Unipolar AI DAC8043 12 bit ...

Page 128: ...it 6 0 425 CALDAC factory constant AO 8800 8 bit 4 0 424 CALDAC factory constant AO 8800 8 bit 7 0 423 CALDAC factory constant AO 8800 8 bit 5 0 422 Factory calibration temperature 371 Start of the five user calibration sections Table 5 2 PCI MIO 16XE 50 EEPROM Map Continued EEPROM Address Data Stored at EEPROM Address Data Type CALDAC Type CALDAC Address Ser DacLd Line ...

Page 129: ...st factory fabrication 431 Factory reference MSB 430 Factory reference LSB 429 CALDAC factory constant MSB Bipolar AI DAC8043 12 bit 1 428 CALDAC factory constant LSB Bipolar AI DAC8043 12 bit 1 427 CALDAC factory constant Bipolar AI 8800 8 bit 2 0 426 CALDAC factory constant Bipolar AI 8800 8 bit 3 0 425 CALDAC factory constant Bipolar AI 8800 8 bit 0 0 424 CALDAC factory constant Bipolar AI 8800...

Page 130: ...4 CALDAC factory constant Bipolar AO 8800 8 bit 5 0 413 CALDAC factory constant Unipolar AO 8800 8 bit 6 0 412 CALDAC factory constant Unipolar AO 8800 8 bit 4 0 411 CALDAC factory constant Unipolar AO 8800 8 bit 7 0 410 CALDAC factory constant Unipolar AO 8800 8 bit 5 0 409 Factory calibration temperature 371 Start of the five user calibration sections 1Board Codes 204 PCI MIO 16XE 10 220 PCI 603...

Page 131: ...n 508 Year of last factory fabrication 507 Month of last factory fabrication 506 Day of last factory fabrication 444 Factory reference MSB 443 Factory reference LSB 442 CALDAC factory constant AI MB88341 8 bit 4 0 441 CALDAC factory constant AI MB88341 8 bit 11 0 440 CALDAC factory constant AI MB88341 8 bit 1 0 439 CALDAC factory constant AI MB88341 8 bit 2 0 438 Factory calibration temperature 37...

Page 132: ...ctory fabrication 506 Day of last factory fabrication 432 Factory reference MSB 431 Factory reference LSB 430 CALDAC factory constant Bipolar AI MB88341 8 bit 4 0 429 CALDAC factory constant Bipolar AI MB88341 8 bit 11 0 428 CALDAC factory constant Bipolar AI MB88341 8 bit 1 0 427 CALDAC factory constant Bipolar AI MB88341 8 bit 2 0 426 CALDAC factory constant Bipolar AO MB88341 8 bit 5 0 425 CALD...

Page 133: ...1 8 bit 9 0 420 Factory calibration temperature 371 Start of the five user calibration sections 1Board Codes LSB MSB 256 LSB Board Code 13 PCI 6024E 1 256 13 269 15 PCI 6025E 1 256 15 271 2 Board Codes MSB 01 PCI 6024E 01 PCI 6025E Table 5 5 PCI 6024E and PCI 6025E EEPROM Map Continued EEPROM Address Data Stored at EEPROM Address Data Type CALDAC Type CALDAC Address Ser DacLd Line ...

Page 134: ... of last factory calibration 416 Factory reference MSB 415 Factory reference LSB 414 CALDAC factory constant AI pregain offset coarse MB88341 0 0 413 CALDAC factory constant AI pregain offset fine MB88341 8 0 412 CALDAC factory constant AI postgain offset coarse MB88341 4 0 411 CALDAC factory constant AI postgain offset fine MB88341 12 0 410 CALDAC factory constant AI gain coarse MB88341 2 0 409 C...

Page 135: ...41 2 1 401 CALDAC factory constant AO1bipolar gain coarse MB88341 10 1 400 CALDAC factory constant AO1bipolar gain fine MB88341 6 1 399 CALDAC factory constant AO1bipolar offset MB88341 14 1 398 CALDAC factory constant AO 0 unipolar linearity MB88341 0 1 397 CALDAC factory constant AO 0 unipolar gain coarse MB88341 8 1 396 CALDAC factory constant AO 0 unipolar gain fine MB88341 4 1 395 CALDAC fact...

Page 136: ...coarse MB88341 10 1 392 CALDAC factory constant AO 1 unipolar gain fine MB88341 6 1 391 CALDAC factory constant AO 1 unipolar offset MB88341 14 1 390 Factory calibration temp 1 371 Start of the four user calibration sections 1 1Board Codes MSB 256 LSB Board Code 1 256 17 267 Table 5 7 Type of CALDAC Used on Board Board MB88341 8 bit DAC8800 8 bit DAC8043 12 bit 1 AD8522 12 bit 2 PCI MIO 16E 1 PCI ...

Page 137: ...rial DACs is similar to the EEPROM The basic write cycle consists of shifting an address data pair into the DAC then pulsing the appropriate SerDacLd pin The timing diagram for the write cycle for each DAC is shown in Figure 5 2 a b c d The serial DAC interface is relatively slow compared to the PCI bus In order to meet the timing specifications of the serial DAC you must double write the clock bi...

Page 138: ...oard for use with Figure 5 2 SerClk a MB 88341 SerDacLd SerData A0 A1 A2 A3 D7 D6 D5 D4 D3 D2 D1 D0 SerClk b DAC 8800 SerDacLd SerData A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SerClk c DAC 8043 SerDacLd SerData D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 SerClk d AD 8522 SerDacLd SerData D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 B A DACA and DACB bits DAC DACB DACA 0 0 1 1 1 0 ...

Page 139: ...Due to the complexity of the actual calibration algorithm use Calibrate_E_Series to calibrate each section and store the results in the EEPROM You can write a separate application using Calibrate_E_Series which is run only when the board needs new calibration constants Writing such an application allows the normal application to simply copy the calibration constants from the EEPROM and write them ...

Page 140: ...s not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrum...

Page 141: ...ffice in your country contact the source from which you purchased your software to obtain support Country Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Brazil 011 288 3336 011 288 8528 Canada Ontario 905 785 0085 905 785 0086 Canada Québec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 725 725 11 0...

Page 142: ...____ Instruments used _________________________________________________________________ _______________________________________________________________________________ National Instruments hardware product model _____________ Revision ____________________ Configuration ___________________________________________________________________ National Instruments software product ___________________ Vers...

Page 143: ...___________ Base memory address of other National Instruments boards _______________________________ Interrupt level of other National Instruments boards _____________________________________ Other Products Computer make and model ________________________________________________________ Microprocessor __________________________________________________________________ Clock frequency or speed _____...

Page 144: ..._____________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ __________________________________________________________...

Page 145: ... 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Symbols inverted bit negative logic if after a bit name Ω ohms A A amperes A D analog to digital AC alternating current ADC A D converter AIGND analog input ground signal AOGND analog output ground signal ASIC application specific integrated circuit ...

Page 146: ...ct bit ChanEnable DMA channel enable bit Channel physical channel select bit ChanType channel type bit CONVERT convert signal D D data bit D A digital to analog DAC D A converter DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DACSe DAC select bit DAQ data acquisition DAR Device Address Register DC direct current DitherEn dither enable bit ...

Page 147: ...l count C bit DmaTcCClr DMA terminal count C clear bit E EEPROM electrically erasable programmable read only memory EEPromCS EEPROM chip select bit EXTREF external reference signal ExtRef external reference for DAC bit EXTSTROBE external strobe signal EXTTRIG external trigger signal F FIFO first in first out G Gain channel gain select bit GenTrig general trigger bit ghost a conversion that is perf...

Page 148: ...xadecimal Hz hertz I I O input output Input analog input bit Int Ext Trig internal external analog trigger IRQ interrupt request signal ISA Industry Standard Architecture ISR interrupt service routine L LASTCHANNEL last channel bit LKAR Link Address Register LSB least significant bit M m meters MAR Memory Address Register MB megabytes of memory ...

Page 149: ...ifiers OS operating system Output analog output bit P PFI0 Trig1 PFI 0 Trigger 1 signal PFI1 Trig2 PFI 1 Trigger 2 signal PGIA Programmable Gain Instrumentation Amplifier ppm parts per million PRETRIG pretrigger signal PROMOUT EEPROM output data bit R ReGlitch reglitch DAC bit RTD resistance temperature detector RTSI Real Time System Integration bus RTSI_BRD0 RTSI board ...

Page 150: ... serial DAC load bit SerData serial data bit SHIFTIN shift in signal SI scan interval counter SI2 sample interval START start signal STOP stop signal T TC terminal count TCIntEnable DMATC interrupt enable bit TCR Transfer Count Register Transfer transfer type bit TTL transistor transistor logic U UC update counter UI update interval ...

Page 151: ...Glossary National Instruments Corporation G 7 PCI E Series RLPM UI2 update interval 2 Unip Bip channel unipolar bipolar bit V V volts Vref input voltage reference X X don t care bits ...

Page 152: ...ple from channel 0 4 10 AMUX 64T examples sampling one channel 4 27 scanning eight channels 4 29 AI_Interrupt_Enable function 4 16 AI_Reset_All function 4 10 AI_Scan_Start function AMUX 64T examples sampling one channel 4 27 scanning eight channels 4 30 sampling from channel 0 4 11 STC scanning examples 4 13 with DMA 4 18 with external start and stop trigger control 4 24 with external start trigge...

Page 153: ...sing local buffer mode 4 41 to 4 43 Analog Output Register Group AO Configuration Register 3 16 to 3 17 DAC FIFO Data Register 3 18 DAC0 Direct Data Register 3 19 DAC1 Direct Data Register 3 20 overview 3 15 register map 3 2 analog output timing circuitry 2 22 to 2 24 single point output 2 22 to 2 23 waveform generation 2 23 to 2 24 analog triggering programming considerations 4 52 to 4 56 example...

Page 154: ... bits AI_FIFO_Empty_St 2 12 Analog_Trigger_Drive 4 53 Bank 1 0 3 12 BipDac 3 17 Chan 3 0 3 12 to 3 15 ChanType 2 0 3 11 D 15 0 3 8 3 18 3 19 3 20 DACSel 3 16 DitherEn 3 9 to 3 10 DOTRIG0 4 52 EEPromCS 3 4 5 1 ExtRef 3 16 to 3 17 Gain 2 0 3 10 GenTrig 3 9 GPCT0 D A 3 23 GPCT1 D A 3 23 GroundRef 3 16 Input D A 3 22 Int Ext Trig 3 5 4 53 LastChan 3 9 LASTCHANNEL 2 10 2 13 Output D A 3 22 PROMOUT 3 6 ...

Page 155: ...nonreferenced single ended channel assignments table 3 13 to 3 14 referenced single ended channel assignments table 3 14 valid channel types table 3 11 ChanType 2 0 bit 3 11 Clear_FIFO function 4 10 4 12 configuration memory definition 2 8 multirate scanning with ghost table 2 18 Configuration Memory Clear Register description 3 24 register map 3 3 Configuration Memory High Register description 3 ...

Page 156: ...a acquisition sequence timing 2 12 to 2 18 multirate scanning with ghost 2 16 to 2 18 advantages figure 2 17 analog input configuration memory table 2 18 occurrences of conversion on channel 1 figure 2 17 successive scans figure 2 17 multirate scanning without ghost 2 14 to 2 16 scanning three channels with 4 2 1 sampling rate figure 2 16 scanning two channels figure 2 15 1 x sampling rate 2 15 3 ...

Page 157: ...mory 2 8 overflow 2 11 theory of operation 2 10 to 2 11 waveform generation 2 23 to 2 24 FIFO Strobe Register Group ADC FIFO Clear Register 3 24 Configuration Memory Clear Register 3 24 DAC FIFO Clear Register 3 24 register map 3 3 FIFO_Request_Selection function 4 58 files for example programs 4 6 FTP support A 1 G G0 G1 Select Register description 3 23 register map 3 2 G0_Arm function buffered p...

Page 158: ...tatus Register 3 6 MITE ASIC initializing PCI 4 2 Link Chaining Mode for DMA transfer 4 58 to 4 59 programming for different DMA transfers 4 20 to 4 21 re mapping PCI E Series board 4 3 MITE_DMAarm function 4 17 4 20 MITE_DMAdisarm function 4 17 4 20 MITE_DMAgettransfsRemaining function 4 20 MITE_DMAProgram function 4 17 4 19 MSC_Clock_Configure function acquiring one sample from channel 0 4 9 con...

Page 159: ...I local bus programming considerations 4 1 to 4 4 PCI initialization for IBM compatible systems 4 2 for Macintosh computers 4 4 re mapping PCI E Series board 4 3 to 4 4 PFIO TRIG1 signal 4 53 PGIA programmable gain instrumentation amplifier analog trigger programming considerations 4 53 gain selection with Gain 2 0 bits 3 10 gain set versus board table 2 9 to 2 10 theory of operation 2 9 posttrigg...

Page 160: ...in generation 4 49 to 4 52 gated event counting 4 45 to 4 47 PROMOUT bit 3 6 5 1 pulse train generation example 4 49 to 4 52 pulsewidth measurement example 4 47 to 4 49 Pulse_Width_Measurement_ISR function 4 48 R referenced single ended channel assignments table 3 14 registers Analog Input Register Group ADC FIFO Data Register 3 8 Configuration Memory High Register 3 11 to 3 15 Configuration Memor...

Page 161: ...up_Mite function analog input examples acquiring one sample from channel 0 4 9 digital I O examples 4 7 general purpose counter timer examples gated event counting 4 45 initializing PCI IBM compatible systems 4 2 Macintosh computers 4 4 re mapping PCI E Series board 4 3 setvect function 4 14 SHIFTIN signal ADC timing 2 12 Simple_Gated_Count function 4 45 single point output analog output timing ci...

Page 162: ... data acquisition 2 11 to 2 18 ADC timing figure 2 12 block diagram 2 8 data acquisition sequence timing 2 12 to 2 18 multirate scanning with ghost 2 16 to 2 18 multirate scanning without ghost 2 14 to 2 16 single read timing 2 11 to 2 12 timing of scan figure 2 14 timing I O circuitry DAQ STC counter diagram 2 24 theory of operation 2 24 to 2 25 trigger lines RTSI 4 52 triggering analog triggerin...

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