National Instruments cDAQ-9179 User Manual Download Page 1

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Summary of Contents for cDAQ-9179

Page 2: ...NI cDAQ TM 9179 User Manual 14 Slot USB 3 0 CompactDAQ Chassis NI cDAQ 9179 User Manual ni com manuals Deutsch Fran ais August 2015 374937A 01...

Page 3: ...ers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support information refer to th...

Page 4: ...ESS FOR A PARTICULAR PURPOSE TITLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING TH...

Page 5: ...es independent from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology re...

Page 6: ...assis on a Rack 1 13 cDAQ Chassis Features 1 14 LEDs 1 14 Chassis Grounding Screw 1 14 PFI 0 and PFI 1 BNC Connectors 1 14 USB 3 0 Port and Cable Strain Relief 1 15 Power Connector 1 15 Cables and Acc...

Page 7: ...Analog Output Triggering Signals 3 3 Analog Output Timing Signals 3 3 AO Sample Clock Signal 3 3 Routing AO Sample Clock to an Output Terminal 3 4 AO Sample Clock Timebase Signal 3 4 AO Start Trigger...

Page 8: ...Width Measurement 5 6 Implicit Buffered Pulse Width Measurement 5 6 Sample Clocked Buffered Pulse Width Measurement 5 7 Pulse Measurement 5 7 Single Pulse Measurement 5 8 Implicit Buffered Pulse Measu...

Page 9: ...cy Generator 5 31 Frequency Division 5 32 Pulse Generation for ETS 5 32 Counter Timing Signals 5 33 Counter n Source Signal 5 33 Routing a Signal to Counter n Source 5 34 Routing Counter n Source to a...

Page 10: ...Prescaling 5 39 Synchronization Modes 5 39 80 MHz Source Mode 5 40 External or Internal Source Less than 20 MHz 5 40 Chapter 6 Digital Routing and Clock Generation Digital Routing 6 1 Clock Routing 6...

Page 11: ...ncluded with your C Series module s or go to ni com manuals Figure 1 1 shows the NI cDAQ 9179 chassis Figure 1 1 NI cDAQ 9179 Chassis Safety Guidelines Caution Do not operate the NI cDAQ 9179 chassis...

Page 12: ...t Caution The NI cDAQ 9179 chassis provides no isolation but some modules offer isolation Follow the safety guidelines for each module when using hazardous voltage Electromagnetic Compatibility Guidel...

Page 13: ...initiatives and compliance with WEEE Directive 2002 96 EC on Waste and Electronic Equipment visit ni com environment weee Unpacking The cDAQ chassis ships in an antistatic package to prevent electrost...

Page 14: ...ation download the Read Me First NI DAQmx and DAQ Device Installation Guide Note NI DAQmx 15 1 is the earliest supported driver version for the cDAQ 9179 The NI DAQmx software is included on the media...

Page 15: ...e module slot and press until both latches lock the module in place 8 Wire the C Series module as indicated in the C Series module documentation Note Connect I O cable shields to the chassis grounding...

Page 16: ...ar press F5 to refresh the view in MAX If your chassis is still not recognized refer to ni com support daqmx for troubleshooting information 13 Self test your chassis in MAX by expanding Devices and I...

Page 17: ...requirements for space and cabling clearance as shown in Figure 1 3 Allow 25 4 mm 1 in on the top and the bottom of the chassis for air circulation Allow 50 8 mm 2 in in front of modules for cabling...

Page 18: ...for convenient access to the C Series module connectors Complete the following steps to install the desktop mounting kit on a chassis You need a 2 Phillips screwdriver to complete installation 1 Use a...

Page 19: ...nd Brackets to the Chassis 4 Use the screwdriver to tighten the captive screw on the end bracket 5 Repeat steps 3 and 4 to attach the other end bracket to the other end of the chassis Figure 1 6 shows...

Page 20: ...M4 21 screws Complete the following steps to install the chassis onto a panel or wall You need a 2 Philips screwdriver to complete the installation 1 Attach the chassis to the panel mounting plate us...

Page 21: ...ditional screws to attach the panel mounting plate to a panel or wall permanently as shown in Figure 1 9 preventing the chassis from being removed Figure 1 9 Permanently Attaching the Panel Mounting P...

Page 22: ...Make sure that no C Series modules are in the chassis before removing it from the surface Mounting the cDAQ Chassis on a DIN Rail Use the NI 9916 DIN rail kit part number 780982 01 to mount the NI cD...

Page 23: ...Diagram Caution Remove the C Series modules before removing the chassis from the DIN rail Mounting the cDAQ Chassis on a Rack NI offers two rack mount kits part numbers 779102 01 and 781989 01 that y...

Page 24: ...wire with a maximum length of 1 5 m 5 ft Attach the wire to the earth ground of the facility s power system For more information about earth ground connections go to ni com info and enter the Info Co...

Page 25: ...a C Series C Series module from the chassis 1 Make sure that no I O side power is connected to the C Series module If the system is in a nonhazardous location the chassis power can be on when you remo...

Page 26: ...stem to meet your application needs C Series modules are hot swappable and automatically detected by the cDAQ chassis I O channels are accessible using the NI DAQmx driver software Because the modules...

Page 27: ...O AI AO and DIO Sample Timing The STC3 contains advanced AI AO and DIO timing engines A wide range of timing and synchronization signals are available through the PFI lines Refer to the following sect...

Page 28: ...chassis slots and through the two PFI terminals provided on the cDAQ chassis Refer to the PFI section of Chapter 4 Digital Input Output and PFI for more information Flexible Counter Timers The cDAQ ch...

Page 29: ...ger is a signal that causes an action such as starting or stopping the acquisition of data When you configure a trigger you must decide how you want to produce the trigger and the action you want the...

Page 30: ...k Timebase signal is divided down to provide a source for Sample Clock AI Sample Clock Timebase can be generated from external or internal sources AI Sample Clock Timebase is not available as an outpu...

Page 31: ...ules in the cDAQ chassis automatically share a single oversample clock to synchronize data from all the modules that support an external oversample clock timebase when they all share the same task DSA...

Page 32: ...task will return 1 000 new data points per second which is normal When performing a single point acquisition no points are repeated To avoid this behavior use multiple AI timing engines and assign sl...

Page 33: ...Start Trigger signal to any output PFI terminal The output is an active high pulse AI Reference Trigger Signal Use Reference Trigger to stop a measurement acquisition To use a reference trigger specif...

Page 34: ...sing or falling edge of the Analog Comparison Event signal depending on the trigger properties Note Depending on the C Series module capabilities you may need two modules to utilize analog triggering...

Page 35: ...high or vice versa Note Depending on the C Series module capabilities you may need two modules to utilize analog triggering Note Pause triggers are only sensitive to the level of the source not the e...

Page 36: ...ods When performing an analog output operation you either can perform software timed or hardware timed generations Hardware timed generations must be buffered Software Timed Generations With a softwar...

Page 37: ...continuous generation continues until you stop the operation There are three different continuous generation modes that control how the data is written These modes are regeneration onboard regenerati...

Page 38: ...nals The cDAQ chassis features the following AO waveform generation timing signals AO Sample Clock Signal AO Sample Clock Timebase Signal AO Start Trigger Signal AO Pause Trigger Signal Signals with a...

Page 39: ...the following signals A pulse initiated by host software Any PFI terminal AI Reference Trigger AI Start Trigger The source also can be one of several internal signals on the cDAQ chassis Refer to the...

Page 40: ...ted and another edge of the sample clock is received as shown in Figure 3 3 Figure 3 3 AO Pause Trigger with Other Signal Source Using a Digital Source To use AO Pause Trigger specify a source and a p...

Page 41: ...r when the most significant bit of the DAC code changes You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of the output signal Go to ni...

Page 42: ...sis slot and can perform the following tasks Software timed and hardware timed digital input output tasks Parallel digital modules can be used in any chassis slot and can perform the following tasks S...

Page 43: ...es of digital triggering internal software digital triggering external digital triggering and internal digital triggering Three triggers are available Start Trigger Reference Trigger and Pause Trigger...

Page 44: ...Sample Clock Timebase Signal The DI Sample Clock Timebase di SampleClockTimebase signal is divided down to provide a source for DI Sample Clock DI Sample Clock Timebase can be generated from external...

Page 45: ...tware command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition That is samples are measured only after th...

Page 46: ...cified number of pretrigger samples the chassis ignores the condition If the buffer becomes full the cDAQ chassis continuously discards the oldest samples in the buffer to make space for the next samp...

Page 47: ...e and a polarity The source can be either from PFI or one of several other internal signals on your cDAQ chassis Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for m...

Page 48: ...ed with DI Applications in Software You can use the cDAQ chassis in the following digital input applications Single point acquisition Finite acquisition Continuous acquisition For more information abo...

Page 49: ...o multiple software timed tasks on a single module as well as mix hardware timed and software timed digital output tasks on a single module On serial digital output modules formerly known as static di...

Page 50: ...a samples and stopping a continuous generation continues until you stop the operation There are three different continuous generation modes that control how the data is written These modes are regener...

Page 51: ...e following DO timing signals DO Sample Clock Signal DO Sample Clock Timebase Signal DO Start Trigger Signal DO Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters...

Page 52: ...ting in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information You also can specify whether the waveform generation begins on the rising edge or falling edge of DO Start Trigger Using...

Page 53: ...polarity The source can be a PFI signal or one of several other internal signals on the cDAQ chassis You also can specify whether the samples are paused when DO Pause Trigger is at a logic high or low...

Page 54: ...k NI DAQmx generates an error instead of sending the line configuration command During the line configuration command the output lines are maintained without glitching PFI You can configure channels o...

Page 55: ...on on an input that has a custom filter set to N 5 Figure 4 7 PFI Filter Example Table 4 1 Selectable PFI Filter Settings Filter Setting Filter Clock Jitter Min Pulse Width to Pass Max Pulse Width to...

Page 56: ...unter signals refer to the Default Counter Timer Routing section Each counter has a FIFO that can be used for buffered acquisition and generation Each counter also contains an embedded counter Embedde...

Page 57: ...son Event Not all timed counter operations require a sample clock For example a simple buffered pulse width measurement latches in data on each edge of a pulse For this measurement the measured signal...

Page 58: ...counter values can be read on demand or with a sample clock Refer to the following sections for more information about edge counting options Single Point On Demand Edge Counting Buffered Sample Clock...

Page 59: ...the number of edges on the Source input after the counter is armed The value of the counter is sampled on each active edge of a sample clock and stored in the FIFO The STC3 transfers the sampled valu...

Page 60: ...route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges on the Source signal while the pulse...

Page 61: ...Width Measurement An implicit buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses The counter co...

Page 62: ...nals refer to the Default Counter Timer Routing section Pulse Measurement In pulse measurements the counter measures the high and low time of a pulse on its Gate input signal after the counter is arme...

Page 63: ...whether to read the high pulse or low pulse first using the StartingEdge property in NI DAQmx Figure 5 9 shows an example of an implicit buffered pulse measurement Figure 5 9 Implicit Buffered Pulse M...

Page 64: ...al with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between two edges of the Gate signal You can calculate...

Page 65: ...versus Semi Period Measurements In hardware pulse measurement and semi period are the same measurement Both measure the high and low times of a pulse The functional difference between the two measurem...

Page 66: ...u can route a known timebase fk to the Source of the counter The known timebase can be an onboard timebase such as 80 MHz Timebase 20 MHz Timebase or 100 kHz Timebase or any other signal with a known...

Page 67: ...asure the width of a known period instead of a known pulse Figure 5 13 High Frequency with Two Counters Large Range of Frequencies with Two Counters By using two counters you can accurately measure a...

Page 68: ...ternal Output signal to the Gate input of Counter 1 You can route a signal of known frequency fk to the Counter 1 Source input Configure Counter 1 to perform a single pulse width measurement Suppose t...

Page 69: ...known frequency fk Suppose T1 is the number of ticks of the unknown signal counted between sample clocks and T2 is the number of ticks counted of the known timebase as shown in Figure 5 15 The freque...

Page 70: ...k rate only used in sample clocked frequency measurements Here is how these variables apply to each method summarized in Table 5 2 One counter With one counter measurements a known timebase is used fo...

Page 71: ...le Clocked One Counter Two Counter High Frequency Large Range fk Known timebase Known timebase Known timebase Measureme nt time gating period Max frequency error fk Max error Note Accuracy equations d...

Page 72: ...the accuracy measurement time and accuracy listed in Table 5 3 But if your signal ramped up to 5 M then with a divide down of 50 your measurement time is 0 01 ms but your error is now 0 125 The error...

Page 73: ...a large range of frequencies with two counters measures high and low frequency signals accurately However it requires two counters and it has a variable sample time and variable error dependent on the...

Page 74: ...g sections for more information about the cDAQ chassis position measurement options Measurements Using Quadrature Encoders Measurements Using Two Pulse Encoders Buffered Sample Clock Position Measurem...

Page 75: ...ns You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B You must then ensure that channel Z is high during at least a portion...

Page 76: ...Measurement With buffered position measurement position measurement using a sample clock the counter increments based on the encoding used after the counter is armed The value of the counter is sampl...

Page 77: ...put The counter stops counting upon receiving an active edge on the Gate input The counter stores the count in the FIFO You can configure the rising or falling edge of the Aux input to be the active e...

Page 78: ...ing or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO On the next active edge...

Page 79: ...rement Note If an active edge on the Gate and an active edge on the Aux does not occur between sample clocks an overrun error occurs For information about connecting counter signals refer to the Defau...

Page 80: ...igure 5 26 Single Pulse Generation Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal The pulse appears on the...

Page 81: ...the primary counter When the embedded counter reaches the specified tick count it generates a trigger that stops the primary counter generation Figure 5 28 Finite Pulse Train Generation Four Ticks Ini...

Page 82: ...ulse train with CO EnableInitalDelayOnRetrigger set to the default False Figure 5 30 Retriggerable Single Pulse Generation False Note The minimum time between the trigger and the first active edge is...

Page 83: ...s equal to the frequency of the Source input divided by M N For information about connecting counter signals refer to the Default Counter Timer Routing section Buffered Pulse Train Generation The cDAQ...

Page 84: ...active times Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation Each point you write generates a single pulse All points are...

Page 85: ...ation the entire buffer must fit within the FIFO size The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started thereby...

Page 86: ...uency Output signal The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16 The Frequency Output Timebase can be either the 20 MHz Timebase the 20 MHz...

Page 87: ...an be between 0 and 255 For instance if you specify the increment to be 10 the delay between the active Gate edge and the pulse on the output increases by 10 every time a new pulse is generated Suppos...

Page 88: ...unter 1 Counter 2 Source the source input to Counter 2 or Counter 3 Source the source input to Counter 3 Note All counter timing signals can be filtered Refer to the PFI Filters section of Chapter 4 D...

Page 89: ...ation about available routing options Routing Counter n Source to an Output Terminal You can route Counter n Source out to any PFI terminal Counter n Gate Signal The Counter n Gate signal can perform...

Page 90: ...e Detection Event In addition a counter s Internal Output Gate or Source can be routed to a different counter s Aux A counter s own gate can also be routed to its Aux input Some of these options may n...

Page 91: ...r to the Counter n HW Arm input of the counter Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input Any PFI terminal AI Reference Trigger...

Page 92: ...ple Clock Routing Counter n Sample Clock to an Output Terminal You can route Counter n Sample Clock out to any PFI terminal The PFI circuitry inverts the polarity of Counter n Sample Clock before driv...

Page 93: ...erations you can use the arm start trigger to have start trigger like behavior The arm start trigger can be used for synchronizing multiple counter input and output tasks When using an arm start trigg...

Page 94: ...aler acts as a frequency divider on the Source and puts out a frequency that is one eighth or one half of what it is accepting as shown in Figure 5 37 Figure 5 37 Prescaling Prescaling is intended to...

Page 95: ...External or Internal Source Less than 20 MHz With an external or internal source less than 20 MHz the module generates a delayed Source signal by delaying the Source signal by several nanoseconds The...

Page 96: ...he acquisition generation sub systems use these signals to manage acquisitions and generations These signals can come from the following sources Your C Series modules User input through the PFI termin...

Page 97: ...al purpose counter timers The 20 MHz Timebase is generated by dividing down the 80 MHz Timebase as shown in Figure 6 1 100 kHz Timebase You can use the 100 kHz Timebase to generate many of the AI and...

Page 98: ...for simulated devices Related Documentation Each application software package and driver includes information about writing applications for taking measurements and controlling measurement devices Th...

Page 99: ...and Functions Describes the LabVIEW NI DAQmx VIs and functions Property and Method Reference NI DAQmx Properties Contains the property reference Taking Measurements Contains the conceptual and how to...

Page 100: ...elp with NI DAQmx methods and properties refer to the NationalInstruments DAQmx namespace and the NationalInstruments DAQmx ComponentModel namespace For conceptual help with NI DAQmx refer to Using th...

Page 101: ...ning courses To enroll in a course or obtain a detailed course outline refer to ni com training Technical Support on the Web For additional support refer to ni com support or ni com examples Note You...

Page 102: ...you identify your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system...

Page 103: ...tions Engineers make sure every question submitted online receives an answer Software Support Service Membership The Standard Service Program SSP is a renewable one year subscription included with alm...

Page 104: ...ications counter input 5 3 counter output 5 24 edge counting 5 3 arm start trigger 5 38 B buffered edge counting 5 4 hardware timed generations analog output 3 2 digital output 4 9 position measuremen...

Page 105: ...ion 4 2 digital input filters parallel DIO modules only 4 6 getting started with applications in software 4 7 timing signals 4 2 triggering 4 2 digital input signals DI Pause Trigger 4 6 DI Reference...

Page 106: ...n software 4 7 DO applications in software 4 13 with the cDAQ chassis 1 1 H hardware timed generations analog output 3 2 digital output 4 9 I implicit buffered pulse width measurement 5 6 semi period...

Page 107: ...ncoders 5 19 R reciprocal frequency measurement 5 12 related documentation A 1 retriggerable single pulse generation 5 26 routing clock 6 1 digital 6 1 S safety guidelines 1 1 for hazardous voltages 1...

Page 108: ...0 kHz 6 2 20 MHz 6 2 80 MHz 6 1 training A 4 TRIG PFI BNC connectors 1 14 trigger arm start 5 38 pause 5 38 start 5 38 two signal edge separation measurement 5 22 buffered 5 23 single 5 23 U unpacking...

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