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Chapter 5
Counters
Pulse Generation for ETS
In the equivalent time sampling (ETS) application, the counter produces a pulse on the output a
specified delay after an active edge on Gate. After each active edge on Gate, the counter
cumulatively increments the delay between the Gate and the pulse on the output by a specified
amount. Thus, the delay between the Gate and the pulse produced successively increases.
The increase in the delay value can be between 0 and 255. For instance, if you specify the
increment to be 10, the delay between the active Gate edge and the pulse on the output increases
by 10 every time a new pulse is generated.
Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200
each time it receives a trigger. Furthermore, suppose you specify the delay increment to be 10.
On the first trigger, your pulse delay will be 100, on the second it will be 110, on the third it will
be 120; the process will repeat in this manner until the counter is disarmed. The counter ignores
any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress.
The waveform thus produced at the counter’s output can be used to provide timing for
undersampling applications where a digitizing system can sample repetitive waveforms that are
higher in frequency than the Nyquist frequency of the system. Figure 5-36 shows an example of
pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent
Gate active edge.
Figure 5-36.
Pulse Generation for ETS
For information about connecting counter signals, refer to the
section.
Counter Timing Signals
The cDAQ controller features the following counter timing signals:
•
•
•
•
•
•
•
OUT
D1
D2 = D1 + DD
D
3
= D1 + 2DD
GATE
