I-6
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National Instruments Corporation
register map, 3-2
Strobes Register, 3-21
DMA programming, 4-53 to 4-55
generating DMA requests, 4-54
single channel vs. dual channel DMA,
4-54 to 4-55
STC scanning with DMA, 4-15 to 4-18
structure (figure), 4-53
DMATCA bit, 3-7
DmaTcAClr bit, 3-21
DMATCB bit, 3-7
DmaTcBClr bit, 3-21
DMATCC bit, 3-7
DmaTcCClr bit, 3-21
documentation
about this manual, ix
conventions used in manual, x-xi
organization of manual, ix-x
related documentation, xi
DOTRIG0 bit, 4-49
E
EEPROM
AT-MIO-16E-1, AT-MIO-16E-2, and
AT-MIO-64E-3 map, 5-2 to 5-4
AT-MIO-16E-10 and AT-MIO-16DE-10
map, 5-4 to 5-5
AT-MIO-16XE-10 and AT-AI-16XE-10
map, 5-7
AT-MIO-16XE-50 map, 5-5 to 5-6
calibration constant storage,
2-10 to 2-11, 5-1
reading from, 5-1 to 5-2
writing to accidentally (note), 5-1
EEPromCS bit, 3-5, 5-1
electronic support services, B-1 to B-2
e-mail support, B-2
ESERFNCT.c example file, 4-4
ESERRLP.h example file, 4-4
event counting example, 4-42 to 4-44
ExtRef bit, 3-17
EXTSTROBE* signal, 2-23 to 2-24
F
fax and telephone support numbers, B-2
Fax-on-Demand support, B-2
FIFO
analog output, 2-21 to 2-22
configuration memory, 2-9
overflow, 2-10
theory of operation, 2-9
waveform generation, 2-23
FIFO Strobe Register Group
ADC FIFO Clear Register, 3-27
Configuration Memory Clear
Register, 3-27
DAC FIFO Clear Register, 3-27
register map, 3-3
FIFO_Request_Selection function, 4-54
files for example programs, 4-4
FTP support, B-1
G
G0 G1 Select Register
description, 3-26
register map, 3-2
G0_Arm function
buffered pulse width measurement
example, 4-44 to 4-46
continuous pulse train generation
example, 4-48
gated event timing example, 4-42
G0_Out_Enable function, 4-48
G0_Reset_All function, 4-42
G0_Seamless_Pulse_Train function, 4-48
G0_Watch function, 4-42
Gain<2..0> bits, 3-11
GATE signal, timing I/O circuitry, 2-24
gated event counting example, 4-42 to 4-44
Summary of Contents for AT-MIO E Series
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