B-32
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ni.com
Appendix B
Timing Diagrams
Figure B-41.
Counter/Timer Circuitry
Pin to Internal Signal Delays
Input timing is the timing specification for importing a signal to an internal bus on the M Series
device. Table B-26 shows the input timing for the counters on all input terminals. Signals refer
to the signal at the I/O connector of the device, and signals appended with _i refer to the signal
internal to the device after the input buffer.
Figure B-42.
Pin to Internal Signal Delays Timing Diagram
Table B-26.
Pin to Internal Signal Delays Timing
Time
From
To
Min (ns)
Max (ns)
t
1
*
PFI
PFI_i
5.2
6.2
18.2
22.0
RTSI
RTSI_i
2.0
2.5
5.0
6.0
STAR
STAR_i
0.9
—
—
2.5
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
3
2-Bit
Co
u
nter
G
a
te
Logic
PFI, RT
S
I,
or PXI_
S
TAR
(Co
u
nter
n
S
o
u
rce)
PFI, RT
S
I,
or PXI_
S
TAR
(Co
u
nter
n
G
a
te)
PFI, RT
S
I,
or PXI_
S
TAR
(Co
u
nter
n
Intern
a
l O
u
tp
u
t)
Co
u
nt_En
ab
le
Other Intern
a
l
S
ign
a
l
s
PFI_i, RT
S
I_i,
or PXI_
S
TAR_i
S
elected_G
a
te
S
elected_
S
o
u
rce
O
u
t_o
PFI, RT
S
I,
or PXI_
S
TAR
8
0 MHz Time
bas
e
20 MHz Time
bas
e
100 kHz Time
bas
e
PXICLK10
t
1
t
1
PFI, RT
S
I,
or PXI_
S
TAR
PFI_i, RT
S
I_i,
or PXI_
S
TAR_i
