Chapter 4
Signal Connections
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National Instruments Corporation
4-23
SCANCLK Signal
SCANCLK is an output-only signal that generates a pulse with the leading
edge occurring approximately 50 to 100 ns after an A/D conversion begins.
The polarity of this output is software-selectable but is typically configured
so that a low-to-high leading edge can clock external analog input
multiplexers indicating when the input signal has been sampled and can be
removed. This signal has a 400 to 500 ns pulse width and is
software-enabled. Figure 4-13
shows the timing for the SCANCLK signal.
Figure 4-13.
SCANCLK Signal Timing
EXTSTROBE* Signal
EXTSTROBE* is an output-only signal that generates either a single pulse
or a sequence of eight pulses in the hardware-strobe mode. An external
device can use this signal to latch signals or to trigger events. In the
single-pulse mode, software controls the level of the EXTSTROBE*
signal. A 10 µs and a 1.2 µs clock are available for generating a sequence
of eight pulses in the hardware-strobe mode. Figure 4-14 shows the timing
for the hardware-strobe mode EXTSTROBE* signal.
Figure 4-14.
EXTSTROBE* Signal Timing
TRIG1 Signal
Any PFI pin can externally input the TRIG1 signal, which is available as
an output on the PFI0/TRIG1 pin. Refer to Figures 4-11 and 4-12 for the
relationship of TRIG1 to the DAQ sequence.
t
w
t
w
= 400 to 500 ns
t
d
= 50 to 100 ns
t
d
CONVERT*
SCANCLK
t
w
t
w
V OH
V OL
t
w
= 600 ns or 5
µ
s
