NI 5762R User Guide and Specifications
12
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8.
Right-click
FPGA Target (RIO
x
, PXI-79
xx
R)
and select
New»FPGA Base Clock again
.
9.
In the
Resource
pull-down menu, select
200 MHz Clock
and click
OK
.
10. Right-click
IO Module
in the
Project Explorer
window and select
Properties
.
11. Select the
NI 5762 (-0
x
)
(where
x
corresponds with the NI part number of your device) from the
IO Module list. The available CLIP for the NI 5762 is displayed in the
General
category of the
Component Level IP pane. If the information in the
General
category is dimmed, select the
Enable
IO Module
checkbox.
12. Select
NI 5762 Multiple Sample CLIP
in the Name list of the Component Level IP section.
13. In the
Clock Selections
category, select
200 MHz Clock
from the pull-down menu for
Clock
200 MHz
. Leave
Clock 40 MHz
configured as the
Top-Level Clock
. This step is necessary to
compile the FPGA VI correctly.
14. Click
OK
.
Note
Configuring these clocks is required for proper CLIP operation. Refer to the NI 5762 CLIP
topics in the
NI FlexRIO Help
for more information about configuring your clocks.
15. In the
Project Explorer
window, right-click the FPGA target and select
New»VI
. A blank VI
opens.
16. Select
Window»Show Block Diagram
to open the VI block diagram.
17. In the
Project Explorer
window, expand the
IO Module (NI 5762 : NI 5762)
tree view.
18. Drag
AI 0 Data N and AI 0 Data N-1
to the block diagram.
19. Add a Timed Loop structure around the two nodes.
20. Wire indicators to the output terminals of the
IO Module\AI 0 Data N
and
IO Module\AI 0 Data
N-1
nodes.
21. Wire an
FPGA Clock Constant
to the input node of the Timed Loop. Set this constant to
IO Module Clock 0
.
Your block diagram should now resemble the block diagram in Figure 6.
Figure 6.
5762SampleAcq (FPGA).vi Block Diagram
Tip
Click the
Clean Up Diagram
button on the toolbar to cleanly organize the VI block diagrams.
22. Save the VI as
5762SampleAcq (FPGA).vi
.
23. Click the
Run
button. LabVIEW creates a default build specification and begins compiling the VI.
The
Generating Intermediate Files
window opens and displays the code generation progress.
Next, the
Compilation Status
window opens and displays the progress of the compilation. The
compilation takes several minutes.
24. Click
Close
in the
Compilation Status
window.
