2-18
IC BLOCK DIAGRAMS & SIGNAL DESCRIPTION
1. U5 (V8601VWA
DVD DSP
)
SIGNAL DESCRIPTION
Signal
I/O Pins
Description
Front End
DSYNC
I
213
DVD parallel mode Sector Sync
DREQ
O
214
DVD parallel mode Data Request
DCLK
I
215
Data sampling clock
DSTB
I
216
Parallel mode Data Valid, serial mode Left/Right Clock
DVD[7:0]
I
*
DVD drive parallel data port, pins: 217, 219-223, 225, 226
External I/O
PCS0
O
193
Peripheral chip select 0, generally used for enabling the program store ROM/FLASH
XIO[14:1]
B
Programmable general purpose I/O also used as peripheral chip select, interrupt, PWM output and other system
signals, pins: 195, 197-200, 202-203, 205-209, 211
SDRAM
MD[31:0]
B
*
SDRAM data bus, pins: 227, 229, 231, 232, 234, 235, 236, 238, 239, 240, 2, 3, 5, 7, 8, 9, 43, 45
46, 48, 50, 51, 52, 54, 55, 56, 58, 59, 60, 61, 63, 64
MA[11:0]
O
*
SDRAM address bus, pins: 12, 13, 15, 16, 18, 20, 21, 25, 26, 28, 29, 30
MA[13:12]
O
32-33
SDRAM address bus, reserved for pin compatibility with 64Mbit SDRAM
MCLK
O
22
SDRAM clock
CKE
O
24
SDRAM Clock Enable
CS0-
O
35
SDRAM primary bank chip select
CS1-
O
66
SDRAM extension bank chip select
RAS-
O
37
SDRAM command bit
CAS-
O
38
SDRAM command bit
WE-
O
39
SDRAM command bit
DQM[3:0]-
O
11, 41,42, 65
SDRAM data byte enables
Host Interface
AD[31:0]
B
*
P multiplexed address/data bus, pins: 136-139, 141-144, 146, 148-153, 155, 157, 158, 163-168, 172-176, 78-180
LA[3:0]
B
184-187
Latched Address [3:0]
ALE
B
183
Address Latch Enable
RD-
B
189
Read
ACK-
B
161
Programmable WAIT-/ACK-/RDY- control
SCLK
O
160
External bus clock used for programmable host bus peripherals
PWE[3:0]-
B
*
Byte write enable for FLASH, EEPROM, SRAM or peripherals, pins: 145, 156, 170, 182
Slave Mode
LHLD
I
191
Bus Hold Request from external master in slave mode
LHLDA
O
190
Bus Hold Acknowledge in slave mode