5
5
&
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&
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&
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&
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&
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&
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&
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&
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&
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9
&
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&
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&
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9
&
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&
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9
&
Q)
&
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&
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9
)%
5
#0
5
.
5
.
5
.
GND
1
8
2
7
3
6
4
5
53
5
[
1
8
2
7
3
6
4
5
53
5
[
1
8
2
7
3
6
4
5
53
5
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1
8
2
7
3
6
4
5
53
5
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1
8
2
7
3
6
4
5
53
5
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1
8
2
7
3
6
4
5
53
5
[
1
8
2
7
3
6
4
5
53
5
[
5
1&
SDA
SCL
PBL
ANK
PHSYN
PVSYN
PCL
K
Y0
Y1
C0
C1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
C2
C3
C4
C5
C6
C7
C8
C9
5
5
5
5
5
5
D+5
V
TX2
+
1
TX2
2
TX2
-
3
TX1
+
4
TX1
5
TX1
-
6
TX0
+
7
TX0
8
TX0
-
9
TC+
10
TC
11
TC-
12
NC
14
DDC_
CL
K
15
DDC_
DT
16
GND
17
VCC
18
HPD
19
G2
20
G1
21
NC
13
3
+'0,
7;
7;
7;
7;
7;
7;
7;
&
7;
&
+3
'
9&&+
'
''&B
'$
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&/
GND
GND
+'0
,
&2
11(&72
5
HSYNC
1
VSYNC
2
CGND
3
CVCC18
4
SPDIF
5
MCLK
6
SD3
7
SD2
8
SD1
9
SD0
10
WS
11
SCK
12
IOVCC
13
IOGND
14
CGND
15
CVCC18
16
INT
17
HPD
18
DSDA
19
DSCL
20
RSVDL
21
PGND1
22
PVCC1
23
EXT_
SW
ING
24
AGND
25
TXC-
26
TXC+
27
AVCC
28
TX0
-
29
TX0
+
30
AGND
31
TX1
-
32
TX1
+
33
AVCC
34
TX2
-
35
TX2
+
36
AGND
37
PVCC2
38
PGND2
39
NC
40
CI2CA
41
RESET#
42
CSCL
43
CSDA
44
CVCC18
45
CGND
46
IOGND
47
IOVCC
48
D23
49
D22
50
D21
51
D20
52
D19
53
D18
54
D17
55
D16
56
D15
57
D14
58
CVCC18
59
CGND
60
D1
3
61
D1
2
62
D1
1
63
D1
0
64
D9
65
IDCK
66
D8
67
D7
68
D6
69
D5
70
IOVCC
71
IOGND
72
CGND
73
CVCC1
8
74
D4
75
D3
76
D2
77
D1
78
D0
79
DE
80
8
6,/
MC
LK
SPDIF
TBCK
TW
SS
TSD0
S
TSD2
S
TSD1
S
TSD3
S
GND
+3
.3
VD
GND
+3
.3
VD
+3
.3
VA
+3
.3
VA
GND
GND
GND
GND
GND
+1
.8
VD
+1
.8
VD
)%
5
#0
GND
+3
.3
VP2
+3
.3
VD
)%
5
#0
+3
.3
VP1
+3
.3
VP2
&
X)
GND
+3
.3
VP1
&
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&
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GND
5
.
5
.
+3
.3
VD
5
.
5
.
'6'$
'6&/
GND
9&&+
'
D+5
V
+3
.3
VD
''&B
'$
''&B
&/
+3
.3
VD
+3
.3
VD
)%
5
#0
+1
.8
VD
1.8V
D
)%
5
#0
+3
.3
VD
3.3V
D
1
8
2
7
3
6
4
5
53
5
[
1
8
2
7
3
6
4
5
53
5
[
5
5
)
P
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PL
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DETECT
R
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VD
GND
&
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GND
&6'$
&6&/
S1
1
G1
2
D2
3
S2
4
G2
5
D1
6
8
83$7
+3
.3
VD
'6
'$
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&/
''&B
'$
''&B
&/
L
INE1
1
L
INE2
9
L
INE3
4
L
INE4
6
NC
2
NC
10
NC
7
NC
5
VCC
3
GND
8
8
5&
/$0
30
L
INE1
1
L
INE2
9
L
INE3
4
L
INE4
6
NC
2
NC
10
NC
7
NC
5
VCC
3
GND
8
8
5&
/$0
30
GND
+3
.3
VD
5
.
.
GND
''&B
'$
''&B
&/
+3
'
L
INE1
1
L
INE2
9
L
INE3
4
L
INE4
6
NC
2
NC
10
NC
7
NC
5
VCC
3
GND
8
8
5&
/$0
30
&(
&+
''&B
'$
''&B
&/
+3
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&(
&+
%
X)
14.DVI CIRCUIT DIAGRAM
3-48
Summary of Contents for M55
Page 26: ...2 SDRAM CLOCK FIG 2 1 3 TRAY OPEN CLOSE SIGNAL CH1 EJ CH2 EJ FIG 3 1 3 12 ...
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