
A. DC OFFSET VOLTAGE
The DC OFFSET between OFFSET Test Point and AGND must be within 0+/-20mV.
B. IDLING CURRENT
The idling current in the output stage of the poweramp should be set to 30mA+/-5mA per
pnp-npn transistor pair (This means the mid point voltage is 6.6mV with down limit of
5.5mV and up limit of 7.7mV). The alignment procedure is: At first, adjust RV102 (Marked
as “Idling Current ADJ” in the drawing below) for a voltage of 6.6mV +/- 1mV between Test
point 1 and 2. Then preheat the unit for 1 minutes, let idling current settled and then readjust
to 6.6mV +/- 1mV. This is a no-load adjustment.
Pls note: Though the idling current is set as 6.6mV +/-1mV during the adjustment, due to the
influence of varied ambient temperature and mains voltage etc., the idling current will drift after
some time. During the normal checking of idling current in the service field, it’s acceptable as
long as the voltage is in the range of 5.5mV—7.7mV
C. ISC SENSITIVITY
The ISC sensing voltage can allow 0mV+/-50mV. But, for the alignment process in our
factory, we tighten the limit to 0mV+/-10mV. That is to adjust Pot RV103 (as marked as
“ISC SENS ADJ” in the below drawing) to get a voltage between the “ISC SENSE TEST
POINT” and AGND to be 0mV+/-10mV.
- 5 -
ALIGNMENT PROCEDURE
Summary of Contents for C275BEEC/AH
Page 1: ...L A U N A M E C I V R E S C275BEE C AH C275BEE H A C STEREO AMPLIFIER STEREO AMPLIFIER...
Page 13: ...13 PCB LAYOUT...
Page 14: ..._ 14 PCB LAYOUT...
Page 15: ..._ _ _ 15 PCB LAYOUT...
Page 16: ...16 PCB LAYOUT 01 37506 00...
Page 17: ..._ _ _ _ _ _ _ _ 17 PCB LAYOUT...
Page 18: ..._ _ _ _ _ _ 18 PCB LAYOUT...
Page 35: ..._ _ _ _ _ _ 35 PACKING DIAGRAM...