MSK MSK5059RH User Manual Download Page 4

 

 

Page 4 of 9 

and plot the loop’s gain and phase response between 1 kHz and 1 MHz. This provides a 
full picture of the situation on both sides of the unity gain frequency (20 kHz in this 
case). Figure 2 illustrates typical results for the default configuration. The phase margin 
is the phase value at the unity gain frequency, or about 68 Deg. The gain margin is the 
gain at the 0° phase frequency, or approximately 32.5dB. 
 

-80

-60

-40

-20

0

20

40

60

80

-200

-150

-100

-50

0

50

100

150

200

10

3

10

4

10

5

10

6

TR

1/

dB

TR
2

f/Hz

TR1: Mag(Gain)

TR2: Phase(Gain)

 

Figure 2 

 

An alternate method is to step the output load and monitor the response of the system to 
the transient. Low pass filtering may be required to remove switching frequency 
components of the signal to make the small transients more visible. A well behaved loop 
will settle back quickly and smoothly (Figure 3-C) and is termed critically damped, 
whereas a loop with poor phase or gain margin will either ring as it settles (Figure 3-B) 
under damped, or take too long to achieve the setpoint (Figure 3-A) over damped. The 
number of rings indicates the degree of stability, and the frequency of the ringing shows 
the approximate unity-gain frequency of the loop. The amplitude of the signal is not 
particularly important, as long as the amplitude is not so high that the loop behaves 
nonlinearly. This method is easy to implement in labs not equipped with network 
analyzers, but it does not indicate gain margin or evidence of conditional stability. In 
these situations, a small shift in gain or phase caused by production tolerances or 
temperature could cause instability even though the circuit functioned properly in 
development. 

 

 

 

 

 

Figure 3-A 

Figure 3-B 

Figure 3-C 

Gain Margin

 

Phase Margin

Summary of Contents for MSK5059RH

Page 1: ...new designs with ample real estate to make changes and evaluate results Evaluation early in the design phase reduces the likelihood of excess ripple instability or other issues from becoming a proble...

Page 2: ...12V When configured for an output voltage of 2 5V or greater the MSK5059RH will function normally with input voltages up to the maximum rating of 15V If operating the MSK5059RH at less than the minimu...

Page 3: ...alues for loop compensation components depend on parameters which are not always well controlled These include inductor value 30 due to production tolerance load current and ripple current variations...

Page 4: ...ansients more visible A well behaved loop will settle back quickly and smoothly Figure 3 C and is termed critically damped whereas a loop with poor phase or gain margin will either ring as it settles...

Page 5: ...logic low to greater than 2 2V with a duty cycle between 10 and 90 The synchronization frequency must be greater than the free running oscillator frequency and less than 1 MHz This means that minimum...

Page 6: ...itance is altered The output contains very narrow voltage spikes because of the parasitic inductance of C5 Ceramic capacitors C6A and B remove these spikes on the demo board In application trace induc...

Page 7: ...DC 2 for 50 DC 90 DC Duty cycle VOUT VIN Maximum output current is then reduced by one half peak to peak inductor current IMAX IP VOUT VIN VOUT 2 L f VIN Example with VOUT 5V VIN 8V DC 5 8 0 625 L 3...

Page 8: ...Switching Frequency Vin 5 0V IOUT 2 0A kHz 500 Output Ripple Voltage Vin 5 0V IOUT 2 0A mVp p 25 Line Regulation 4 3V Vin 15V IOUT 2 0A 0 1 Load Regulation Vin 5 0V IOUT 50mA to 2 0A 0 3 Efficiency V...

Page 9: ...CWR29FC227K C5B 220 uF Low ESR tantalum AVX TAZH227K010L CWR29FC227K C5C 220 uF Low ESR tantalum AVX TAZH227K010L CWR29FC227K C5D N A C5E N A C5F N A C6A 1210 Ceramic cap 1 0uF AVX 12103C105KAT C6B 8...

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