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AN017 

6

 

Figure 4 illustrates the typical results for a critically damped step load response between  

500ma and 1.0A. 

 

 

Figure 4 (Typical Step Response) 

 
Current Sharing and Synchronization 
 

There are several advantages to using a multiple switcher approach compared to a single 
larger switcher. The inductor size is considerably reduced. Three 2A inductors store less 
energy (LI

2

/2) than one 6A inductor so are far smaller. In addition, synchronizing three 

converters 120° out of phase with each other reduces input and output ripple currents. This 
reduces the ripple rating, size and cost of filter capacitors. If the SYNC pin is not used in the 
application, tie it to ground. To synchronize switching to an external clock, apply a logic-
level signal to the SYNC pin. The recommended clock source is a square-wave with 20% to 
80% duty cycle. The clock source rise and fall times must be faster than 1uS. The 
Synchronization range is from 250KHz to 2.4MHz. The RT pin resistor must be set to a 
frequency which is 20% below the lowest synchronized frequency. Reference the PGOOD 
pin description. It is important to note that slope compensation is set by the RT value: When 
the sync frequency is much higher than the one set by RT, the slope compensation will be 
significantly reduced which may require a larger inductor value to prevent subharmonic 
oscillation. 

 
PGOOD Pin 

 
The PGOOD pin is an open collector output driven by a comparator with a 0.7V reference 
and the FB pin as its input. PGOOD is a low until the FB pin is 86% of its final voltage. For 
PGOOD to be valid VIN must be greater than 3.6V and the RUN/SS pin must be high. A 
high level on the PGOOD pin also indicates the regulator is ready for switching frequency 
synchronization at the SYNC pin. 
 

RUN/SS 

 
The RUN/SS pin provides for shutting the regulator down and soft-start control. Less than 
0.2V on the RUN/SS pin shuts down the regulator. If the RUN/SS pin is greater than 2.5V, 
the regulator runs in normal mode. Soft-start control is achieved by adding a RC network on 
the RUN/SS pin. The voltage ramp on the RUN/SS pin limits the current during startup to 
minimize startup surge current and output overshoot. Tie RUN/SS to VIN if shutdown and 
soft-start are not required. 

Summary of Contents for MSK5031

Page 1: ...om which to evaluate new designs with ample real estate to make changes and evaluate results Evaluation early in the design phase reduces the likelihood of excess ripple instability or other issues from becoming a problem at the application PCB level This application note is intended to be used in conjunction with the MSK5031 data sheet and the LT3480 data sheet Reference those documents for addit...

Page 2: ...ut Voltage Programming VOUT VFB 1 R1 R2 R1 R2 VOUT VFB 1 Given VREF 0 79V Typ Factory Configuration R1 8 98K R2 10 0K VOUT 0 79 1 8 98K 10 0K 1 499V Switching Frequency Programming The operating frequency is programmed by the value of RT The value for RT will vary from 187k at 200 kHz to 8 66k at 2 4 MHz based on the application requirements Higher operating frequencies require smaller inductor an...

Page 3: ... overall efficiency Connect a capacitor between Boost and SW to store a charge A boost pin voltage of at least 2 3V relative to the SW pin is required throughout the on time of the switch to guarantee that it remains saturated Capacitor C2 and an internal boost Schottky diode are used to generate a boost voltage that is higher than the input voltage In most cases a 0 22μF capacitor will work well ...

Page 4: ...sure that it is stable and tolerant of all these variations Phase margin and gain margin are measures of stability in closed loop systems Phase margin indicates relative stability and whether or not there is a tendency to oscillate during its damped response to an input change such as a step function Moreover the phase margin measures how much phase variation is needed at the gain crossover freque...

Page 5: ... setpoint Figure 3 A over damped The number of rings indicates the degree of stability and the frequency of the ringing shows the approximate unity gain frequency of the loop The amplitude of the signal is not particularly important as long as the amplitude is not so high that the loop behaves nonlinearly This method is easy to implement in labs not equipped with network analyzers but it does not ...

Page 6: ...he lowest synchronized frequency Reference the PGOOD pin description It is important to note that slope compensation is set by the RT value When the sync frequency is much higher than the one set by RT the slope compensation will be significantly reduced which may require a larger inductor value to prevent subharmonic oscillation PGOOD Pin The PGOOD pin is an open collector output driven by a comp...

Page 7: ...ESR by choosing a different capacitor or placing more capacitors in parallel For very low ripple an additional LC filter in the output may be a more suitable solution Re compensation of the loop may be required if the output capacitance is altered The output contains very narrow voltage spikes caused by the parasitic inductance of C5 Ceramic capacitors C6A and B remove these spikes on the demo boa...

Page 8: ...converter is limited by the maximum switch current rating This current rating is at least 3 5A for lower duty cycles and decreases linearly to 3 0A at a duty cycle of 0 8 for the MSK5031 Figure 5 Maximum output current is then reduced by one half peak to peak inductor current IMAX IP VOUT VIN VOUT 2 L f VIN Example given VOUT 5V VIN 8V DC 5 8 0 625 L 4 7µH IP 3 2A Figure 5 IMAX 3 2A 5V 8V 5V 2 4 7...

Page 9: ... Default Switching Frequency Vin 5 0V IOUT 1 0A kHz 781 Output Ripple Voltage Vin 5 0V IOUT 1 0A mVp p 7 Line Regulation 5V Vin 15V IOUT 1 0A 0 04 Load Regulation Vin 5 0V IOUT 5A to 2 0A 0 09 Efficiency Vin 5 0V IOUT 1 0A 72 4 Gain Margin Vin 5 0V IOUT 2 0A dB 32 4 Phase Margin Vin 5 0V IOUT 2 0A Deg 81 6 MSK5031 Evaluation Board PCB Layout Artwork Top Side Bottom Side ...

Page 10: ... C5B 47 uF Low ESR tantalum AVX TAZF476K010L CWR29FC476K C5C NP C5D NP C5E NP C5F NP C6A 1210 Ceramic cap 1 0uF AVX 12101C105K C6B 8050 Ceramic cap 0 1uF AVX 08051C104K C7 8050 Ceramic Cap 150pF AVX 08055A151K C8 8050 Ceramic Cap 0 015uF AVX 08055C153K C9 NP C10 NP C11 NP R1 Resistor 8 98K 1 8W R2 Resistor 10 0K 1 8W R3 Resistor 18 2K 1 8W R4 Resistor 20Ω 1 8W R5 Resistor 40 2K 1 8W R6 Resistor 49...

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