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M S-6427 Barebone
3-14
CPU & PCI Bus Control
Press <Enter> and the following sub-menu appears:
PCI Master 0 WS Write
W hen [Enabled], writes to the PCI bus are executed with zero wait
states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select [Enabled] to support compliance with
PCI specification version 2.1.
VLink mode selection
This item lets you choose the speed mode between the North Bridge &
South Bridge.
VLink 8X Support
This item enables or disables the 8X VLink Data Rate.
DRDY_Timing
This item allows you to select the DRDY Timing from Slowest, Default
and Optimize.