MOTOROLA
MC68HC11F1/FC0
60
MC68HC11FTS/D
TICx registers are not affected by reset.
All TOCx register pairs are reset to ones ($FFFF).
TI4/O5 is reset to ones ($FFFF).
OM2–OM5 — Output Mode
OL2–OL5 — Output Level
Each OMx–OLx bit pair determines the output action taken on the corresponding OCx pin after a suc-
cessful compare, as shown in Table 29. OC5 functions only if the I4/O5 bit in the PACTL register is
cleared.
TIC1–TIC3 — Timer Input Capture $x010–$x015
$x010
Bit 15
14
13
12
11
10
9
Bit 8
High
$x011
Bit 7
6
5
4
3
2
1
Bit 0
Low
$x012
Bit 15
14
13
12
11
10
9
Bit 8
High
$x013
Bit 7
6
5
4
3
2
1
Bit 0
Low
$x014
Bit 15
14
13
12
11
10
9
Bit 8
High
$x015
Bit 7
6
5
4
3
2
1
Bit 0
Low
TOC1–TOC4 — Timer Output Compare $x016–$x01D
$x016
Bit 15
14
13
12
11
10
9
Bit 8
High
$x017
Bit 7
6
5
4
3
2
1
Bit 0
Low
$x018
Bit 15
14
13
12
11
10
9
Bit 8
High
$x019
Bit 7
6
5
4
3
2
1
Bit 0
Low
$x01A
Bit 15
14
13
12
11
10
9
Bit 8
High
$x01B
Bit 7
6
5
4
3
2
1
Bit 0
Low
$x01C
Bit 15
14
13
12
11
10
9
Bit 8
High
$x01D
Bit 7
6
5
4
3
2
1
Bit 0
Low
TI4/O5 — Timer Input Capture 4/Output Compare 5 $x01E,
$x01F
$x01E
Bit 15
14
13
12
11
10
9
Bit 8
High
$x01F
Bit 7
6
5
4
3
2
1
Bit 0
Low
TCTL1 — Timer Control 1
$x020
Bit 7
6
5
4
3
2
1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
0
0
0
0
0
0
0
0
