Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 90 / 150

Obtaining Results from the Power-On Self-Test Firmware
4 - 26 PPC/PMC-8260/DS1
Checksum
The checksum word contains the sum of all other POST result words. Before eval-
uating the POST results the software must calculate this checksum and verify it
against the checksum word. If the checksum does not match, no POST has been
executed.
POST Progress Information
Provided that the PCR[INI] bit is set (see the “Controlling Boot Process” section on
page 4-13), the POST uses mailbox register 5 of the PowerSpan II (offset 464
16
) to
pass information to the host which test is currently being executed. In this context
this register is referred to as the test status register (TSR).
When a particular test is ongoing the corresponding bit as defined in table 16
“POST Result and Status Bits” on page 4-25 is set. All other bits are cleared. A val-
ue of zero indicates that the POST is either complete or a test has been completed
and the next test is about to be started.
The TSR can be used to monitor the progress of the POST and to see what the last
test was that has been executed in case of a fatal error.
Device-Specific Results
More detailed information on the tests performed on each device are stored in the
test result words. Each bit set in one of these words indicates a specific operation
which failed.
In general, a test result word of FFFFFFFF
16
indicates a device that is either not as-
sembled or could not be accessed. Only the latter case is indicated as error in the
PRC.
10 Set to 1 if the SDRAM passed all tests
11 Set to 1 if the SSRAM passed all tests
Table 16: POST Result and Status Bits (cont.)
Offset: 00
16
Bit Description