Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 89 / 150

Firmware Obtaining Results from the Power-On Self-Test
PPC/PMC-8260/DS1 4 - 25
The POST information is stored in the following twelve 32-bit words:
Table 15: POST Result Storage Area
Offset Relative to Dual-Ported RAM: B800
16
Offset (hex) Content
00 POST result code (PRC)
04 Checksum
08 SDRAM test results
0C SSRAM test results
10 PowerSpan II test results
14 Framer #1 test results
18 Framer #2 test results
1C Framer #3 test results
20 Framer #4 test results
24 Lucent T8105 test results
28 Reserved (zero)
2C Reserved (zero)
Global Results
The POST result code (PRC) is set and each bit represents one of the eight tests
being executed, plus an additional “global POST failure” bit (0).
Table 16: POST Result and Status Bits
Offset: 00
16
Bit Description
0 (lsb) POST Failure. Set to 1 if at least one device failed the tests
1..3 Not used
4 Set to 1 if framer #1 passed all tests
5 Set to 1 if framer #2 passed all tests
6 Set to 1 if framer #3 passed all tests
7 Set to 1 if framer #4 passed all tests
8 Set to 1 if the T8105 passed all tests
9 Set to 1 if the PowerSpan II PCI bridge passed all tests