Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 88 / 150

Obtaining Results from the Power-On Self-Test Firmware
4 - 24 PPC/PMC-8260/DS1
Obtaining Results from the Power-On Self-Test
While the POST is running, the firmware stores the results of each test in the dual-
ported RAM of the PowerQUICC II. Progress is indicated via:
• Front panel LEDs (see the “LED States During Power Up” section page 3-5)
• Mailbox register 5 of the PowerSpan II (offset 464
16
, see section “POST
Result Storage Area” on page 4-24)
Since the POST does not halt if it detects errors your application software should
evaluate the POST results written into mailbox register 5 of the PowerSpan II as
soon as possible. Otherwise, a fatal error while the POST is running will cause the
software watchdog timer to expire and reset the board.
Requirements
POST results are obtained via the primary booter. In order to evaluate the POST re-
sults, your driver has to include at least the programming routines for:
• Starting the pimary booter
Program your software according to the description on page 4-33.
• Reading and writing
Program your software according to the description on page 4-22.
• Reading POST results
For a code example, see page 4-38.
For information on the primary booter’s communication window, commands, pa-
rameters, and command programming conventions, refer to section “Primary
Booter” on page 4-15.
POST Result Storage Area
The POST stores information on its progress and the results in bank 12 of the inter-
nal dual-ported RAM of the PowerQUICC II. The offset relative to the IMMR is
B800
16
, resulting in the absolute address of F000B800
16
in the memory map of the
PPC/PMC-8260/DS1.