Motorola PPC/CPCI-690, Reference Manual

Page: 155 / 176

Maps and Registers Interrupt Map
PPC/CPCI-690 6 - 7
The following table gives an overview on the MPP configuration for the
board.
MPP Control 2 F100F008
16
00000000
16
MPP Control 3 F100F00C
16
00000000
16
GPP I/O Control F100F100
16
00000000
16
GPP Level Control F100F110
16
FFC7C000
16
Table 28: MPP and GPP Register Settings
Register Address Data
Table 29: System Controller MPP Configuration
MPP Function Description Direction Polarity
[31]
[30]
[29]
[28] GPP[31]
GPP[30]
GPP[29]
GPP[28] PCI bus 1 interrupts Input Active low
[27]
[26]
[25]
[24] GPP[27]
GPP[26]
GPP[25]
GPP[24] PCI bus 0 interrupts Input Active low
[23] GPP[23] Watchdog interrupt (in) Input Active low
[22] GPP[22] Reserved Input Active low
[21]
[20]
[19] GPP[21]
GPP[20]
GPP[19] IPMI interrupts Input Active high
[18] GPP[18] Ejector interrupt Input Active low
[17] GPP[17] CompactPCI interrupt DEG# Input Active low
[16] GPP[16] CompactPCI interrupt FAL# Input Active low
[15] GPP[15] Reserved Input Active low
[14] GPP[14] Reserved Input Active low
[13] INT#[1] PowerPC interrupt SMI# Output Active low
[12] INT#[0] PowerPC interrupt MCP# Output Active low
[11] WDE# Watchdog expired reset Output Active low
[10] WDNMI# Watchdog interrupt Output Active low
[9] REQ0[4]# PCI bus 0 REQ# Input Active low