Motorola PowerPC MPC750 User Manual Download Page 41

Page: 41 / 468

Summary of Contents for PowerPC MPC750

Page 1: ......

Page 2: ...MPC750 Rise Microprocessor User s Manual MPC750UM AD 8 97 MOTOROLA ...

Page 3: ...hnical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where p...

Page 4: ...on Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation L2 Cache Interface Operation Power and Thermal Management Performance Monitor PowerPC Instruction Set Listings _ Instructions Not Implemented _ Glossary of Terms and Abbreviations Index ...

Page 5: ...on Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation L2 Cache Interface Operation Power and Thermal Management Performance Monitor PowerPC Instruction Set Listings Instructions Not Implemented III Glossary of Terms and Abbreviations Index ...

Page 6: ...eatures 1 4 Instruction Flow 1 7 Instruction Queue and Dispatch Unit 1 8 Branch Processing Unit BPU 1 8 Completion Unit 1 9 Independent Execution Units 1 10 Integer Units IUs 1 10 Floating Point Unit FPU 1 10 Load Store Unit LSU 1 11 System Register Unit SRU 1 11 Memory Management Units MMUs 1 12 On Chip Instruction and Data Caches 1 13 L2 Cache Implementation Not Supported in the MPC740 1 14 Syst...

Page 7: ...fic Registers 2 8 Instruction Address Breakpoint Register IABR 2 8 Hardware Implementation Dependent Register 0 2 9 Hardware Implementation Dependent Register 1 2 13 Performance Monitor Registers 2 14 Monitor Mode Control Register 0 MMCRO 2 14 User Monitor Mode Control Register 0 UMMCRO 2 1S Monitor Mode Control Register 1 MMCRl 2 16 User Monitor Mode Control Register 1 UMMCRl 2 16 Performance Mon...

Page 8: ...ed Exceptions 2 37 Instruction Set Overview 2 37 PowerPC UISA Instmctions 2 38 Integer Instmctions 2 38 Integer Arithmetic Instmctions 2 38 Integer Compare Instmctions 2 39 Integer Logical Instmctions 2 40 Integer Rotate and Shift Instmctions 2 40 Floating Point Instmctions 2 41 Floating Point Arithmetic Instmctions 2 42 Floating Point Multiply Add Instmctions 2 42 Floating Point Rounding and Conv...

Page 9: ...n Instructions VEA 2 61 Memory Control Instructions VEA 2 62 User Level Cache Instructions VEA 2 62 Optional External Control Instructions 2 64 PowerPC OEA Instructions 2 65 System Linkage Instructions OEA 2 65 Processor Control Instructions OEA 2 65 Memory Control Instructions OEA 2 66 Supervisor Level Cache Management Instruction OEA 2 66 Segment Register Manipulation Instructions OEA 2 67 Trans...

Page 10: ...16 Data Cache Block Flush debt 3 17 Data Cache Block Invalidate debi 3 17 Instruction Cache Block Invalidate icbi 3 17 Cache Operations 3 18 Cache Block Replacement Castout Operations 3 18 Cache Flush Operations 3 21 Data Cache Block Fill Operations 3 21 Instruction Cache Block Fill Operations 3 21 Data Cache Block Push Operation 3 22 Enveloped High Priority Cache Block Push Operation 3 22 Ll Cach...

Page 11: ...l Exception OxOOCOO 4 19 Trace Exception OxOODOO 4 19 Floating Point Assist Exception OxOOEOO 4 20 Performance Monitor Interrupt OxOOFOO 4 20 Instruction Address Breakpoint Exception Ox01300 4 21 System Management Interrupt Ox01400 4 22 Thermal Management Interrupt Exception Ox01700 4 24 Chapter 5 Memory Management MMU Overview 5 2 Memory Addressing 5 4 MMU Organization 5 4 Address Translation Mec...

Page 12: ... Arbitration 6 11 Cache Hit 6 11 Cache Miss 6 14 L2 Cache Access Timing Considerations MPC750 Only 6 15 Instruction Dispatch and Completion Considerations 6 16 Rename Register Operation 6 17 Instruction Serialization 6 17 Execution Unit Timings 6 18 Branch Processing Unit Execution Timing 6 18 Branch Folding and Removal of Fall Through Branch Instructions 6 18 Branch Instructions and Completion 6 ...

Page 13: ... Bus Arbitration Signals 7 4 Bus Request BR Output 7 4 Bus Grant BG Input 7 4 Address Bus Busy ABB 7 5 Address Bus Busy ABB Output 7 5 Address Bus Busy ABB Input 7 5 Address Transfer Start Signals 7 6 Transfer Start TS 7 6 Transfer Start TS Output 7 6 Transfer Start TS Input 7 6 Address Transfer Signals 7 6 Address Bus A 0 31 7 7 Address Bus A 0 31 Output 7 7 Address Bus A 0 31 Input 7 7 Address B...

Page 14: ... Bus DH 0 31 DL 0 31 7 17 Data Bus DH 0 31 DL 0 31 Output 7 17 Data Bus DH 0 31 DL 0 31 Input 7 18 Data Bus Parity DP 0 7 7 18 Data Bus Parity DP 0 7 Output 7 18 Data Bus Parity DP 0 7 Input 7 18 Data Bus Disable DBDIS Input 7 19 Data Transfer Termination Signals 7 19 Transfer Acknowledge TA Input 7 19 Data Retry DRTRY Input 7 20 Transfer Error Acknowledge TEA Input 7 20 System Status Signals 7 21...

Page 15: ...Signals 7 29 System Clock SYSCLK Input 7 29 Clock Out CLK_OUT Output 7 29 PLL Configuration PLL_CFG 0 3 Input 7 30 Power and Ground Signals 7 30 Chapter 8 System Interface Operation MPC750 System Interface Overview 8 1 Operation of the Instruction and Data Ll Caches 8 2 Operation of the L2 Cache 8 4 Operation of the System Interface 8 4 Direct Store Accesses 8 5 Memory Access Protocol 8 6 Arbitrat...

Page 16: ... 8 34 No DRTRY Mode 8 34 Interrupt Checkstop and Reset Signals 8 35 External Interrupts 8 35 Checkstops 8 35 Reset Inputs 8 35 System Quiesce Control Signals 8 35 Processor State Signals 8 36 Support for the lwarxlstwcx Instruction Pair 8 36 TLBISYNC Input 8 36 IEEE 1149 1a 1993 Compliant Interface 8 37 JTAG COP Interface 8 37 Using Data Bus Write Only 8 37 Chapter 9 L2 Cache Interface Operation L...

Page 17: ...Operation 10 8 TAU Single Threshold Mode 10 8 TAU Dual Threshold Mode 10 9 MPC750 Junction Temperature Determination 10 10 Power Saving Modes and TAU Operation 10 10 Instruction Cache Throttling l0 10 Chapter 11 Performance Monitor Performance Monitor Interrupt 11 2 Special Purpose Registers Used by Performance Monitor 11 3 Performance Monitor Registers 11 3 Monitor Mode Control Register 0 MMCRO 1...

Page 18: ... A I Instructions Sorted by Mnemonic A I A 2 Instructions Sorted by Opcode A 9 A 3 Instructions Grouped by Functional Categories A I7 AA Instructions Sorted by Form A 29 A 5 Instruction Set Legend A 4I Contents Appendix B Instructions Not Implemented Glossary of Terms and Abbreviations xv ...

Page 19: ...xvi MPC750 RISC Microprocessor User s Manual ...

Page 20: ...A 2 20 Instruction Cache Throttling Control Register ICTC 2 21 Thermal Management Registers 1 2 THRMl THRM2 2 22 Thermal Management Register 3 THRM3 2 23 L2 Cache Control Register L2CR 2 24 Cache Integration 3 2 Data Cache Organization 3 4 Instruction Cache Organization 3 5 MEl Cache Coherency Protocol State Diagram WIM 00l 3 8 PLRU Replacement Algorithm 3 19 Double Word Address Ordering Critical ...

Page 21: ... Cycle withARTRY 8 19 Data Bus Arbitration 8 20 Normal Single Beat Read Termination 8 23 Normal Single Beat Write Termination 8 23 Normal Burst Transaction 8 24 Termination with DRTRY 8 25 Read Burst with TA Wait States and DRTRY 8 25 MEl Cache Coherency Protocol State Diagram WIM 001 8 27 Fastest Single Beat Reads 8 28 Fastest Single Beat Writes 8 29 Single Beat Reads Showing Data Delay Controls ...

Page 22: ... Read Write Write L2 Cache Access Late Write SRAM 9 14 10 1 Thermal Assist Unit Block Diagram 10 6 11 1 Monitor Mode Control Register 0 MMCRO 11 4 11 2 Monitor Mode Control Register 1 MMCRl 11 5 11 3 Performance Monitor Counter Registers PMC1 PMC4 11 6 11 4 Sampled instruction Address Registers SIA 11 10 Illustrations xix ...

Page 23: ...xx MPC750 RISC Microprocessor User s Manual ...

Page 24: ...s 2 9 HIDO BCLK and HIDO ECLK CLK_OUT Configuration 2 13 HIDI Bit Functions 2 13 MMCRO Bit Settings 2 14 MMCRI Bit Settings 2 16 PMCn Bit Settings 2 17 PMCI Events MMCRO l9 25 Select Encodings 2 17 PMC2 Events MMCRO 26 31 Select Encodings 2 18 PMC3 Events MMCRl O 4 Select Encodings 2 18 PMC4 Events MMCR1 5 9 Select Encodings 2 19 ICTC Bit Settings 2 21 THRMI THRM2 Bit Settings 2 22 Valid THRMlITHR...

Page 25: ...ISA 2 56 2 48 PowerPC Encodings 2 56 2 49 SPR Encodings for MPC750 Defined Registers mfspr 2 58 2 50 Memory Synchronization Instructions UISA 2 59 2 51 Move from Time Base Instruction 2 60 2 52 Memory Synchronization Instructions VEA 2 62 2 53 User Level Cache Instructions 2 63 2 54 External Control Instructions 2 64 2 55 System Linkage Instructions OEA 2 65 2 56 Move to from Machine State Registe...

Page 26: ...18 MPC750 Microprocessor Instruction Summary Control MMUs 5 19 MPC750 Microprocessor MMU Registers 5 20 Table Search Operations to Update History Bits TLB Hit Case 5 22 Model for Guaranteed Rand C Bit Settings 5 24 Performance Effects of Memory Operand Placement 6 26 TLB Miss Latencies 6 28 Branch Instructions 6 31 System Register Instructions 6 31 Condition Register Logical Instructions 6 32 Inte...

Page 27: ...ting Point Multiply Add Instructions A 20 Floating Point Rounding and Conversion Instructions A 2I Floating Point Compare Instructions A 2I Floating Point Status and Control Register Instructions A 2I Integer Load Instructions A 22 Integer Store Instructions A 23 Integer Load and Store with Byte Reverse Instructions A 23 Integer Load and Store Multiple Instructions A 23 Integer Load and Store Stri...

Page 28: ...ber Title XL Form A 36 XFX Form A 36 XFL Form A 37 XS Form A 37 XO Form A 37 A Form A 38 M Form A 39 MD Form A 39 MDS Form A 40 PowerPC Instruction Set Legend A 41 32 Bit Instructions Not Implemented by the MPC750 Processor B 1 64 Bit Instructions Not Implemented by the MPC750 Processor B 1 xxv ...

Page 29: ...xxvi MPC750 RISC Microprocessor User s Manual ...

Page 30: ... a broad range of processors The Programming Environments Manual provides a general description of features that are common to PowerPC processors and indicates those features that are optional or that may be implemented differently in the design of each processor Note that The Programming Environments Manual exists in two versions PowerPC Microprocessor Family The Programming Environments Rev 1 de...

Page 31: ...ecessarily adhere to the OEA PowerPC operating environment architecture OEA The OEA defines supervisor level resources typically required by an operating system The OEA defines the PowerPC memory management model supervisor level registers and the exception modeL Implementations that conform to the PowerPC OEA also conform to the PowerPC urSA and VEA It is important to note that some resources are...

Page 32: ...ul for readers who want a general understanding of the features and functions of the PowerPC architecture and the MPC750 This chapter describes the flexible nature of the PowerPC architecture definition and provides an overview of how the PowerPC architecture defines the register set operand conventions addressing modes instruction set cache model exception model and memory management model Chapte...

Page 33: ...if the instruction is 64 bit and optional Appendix B Instructions Not Implemented provides a list of the 32 bit and 64 bit PowerPC instructions that are not implemented in the MPC750 This manual also includes a glossary and an index Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC ar...

Page 34: ...C603EUM AD Motorola order PowerPC 604 RISC Microprocessor User s Manual MPC604UM AD Motorola order Programming environments manuals These books provide information about resources defined by the PowerPC architecture that are common to PowerPC processors There are two versions one that describes the functionality of the combined 32 and 64 bit architecture models and one that describes only the 32 b...

Page 35: ...ola order PowerPC 604 RISC Microprocessor Hardware Specifications MPC604ECID Motorola order PowerPC 604e RISC Microprocessor Family PID9V 604e Hardware Specifications MPC604E9VECID Motorola order Technical Summaries Each PowerPC implementation has a technical summary that provides an overview of its features This document is roughly the equivalent to the overview Chapter 1 of an implementation s u...

Page 36: ...eing released as new processors become available For a current list of PowerPC documentation refer to the world wide web at http www motorola com PowerPCI Conventions This document uses the following notational conventions mnemonics italics OxO ObO rA rB rD frA frB frC frD REG FIELD x n AboutThis Book Instruction mnemonics are shown in lowercase bold Italics indicate variable command parameters fo...

Page 37: ... Bus interface unit BPU Branch processing unit BTIC Branch target instruction cache BSDL Boundary scan description language BUID Bus unit 10 CMOS Complementary metal oxide semiconductor COP Common on chip processor CR Condition register CO Completion queue CTR Count register DABR Data address breakpoint register DAR Data address register DBAT Data BAT DCMP Data TLB compare DEC Decrementer register...

Page 38: ...ttling control register IEEE Institute for Electrical and Electronics Engineers IMMU Instruction MMU IQ Instruction queue ITLB Instruction translation lookaside buffer IU Integer unit JTAG Joint Test Action Group L2 Secondary cache Level 2 cache L2GR L2 cache control register LIFO Last in first out LR Link register LRU Least recently used LSB Least significant byte Isb Least significant bit LSU Lo...

Page 39: ... instruction set computing RTL Register transfer language RWITM Read with intent to modify RWNITM Read with no intent to modify SDA Sampled data address register SDR1 Register that specifies the page table base address for virtual to physical address translation SIA Sampled instruction address register SPR Special purpose register SRn Segment register SRU System register unit SRRO Machine status s...

Page 40: ...ons such as carries and overflows for integer operations Terminology Conventions Table ii describes terminology conventions used in this manual and the equivalent terminology used in the PowerPC architecture specification Table ii Terminology Conventions The Architecture Specification This Manual Data storage interrupt OSI OSI exception Extended mnemonics Simplified mnemonics Fixed point unit FXU ...

Page 41: ...Architecture Specification Equivalent to BA BB BT crbA crbB crbO respectively BF BFA crfO crfS respectively 0 d OS ds FLM FM FRA FRB FRC FR FRS frA frB frC frO frS respectively FXM CRM RA RB RT RS rA rB rO rS respectively SI SIMM U IMM UI UIMM I II III 0 0 shaded xxxviii MPC750 RISC Microprocessor User s Manual ...

Page 42: ...It incorporates the following six execution units Floating point unit FPU Branch processing unit BPU System register unit SRU Load store unit LSU Two integer units IUs lUI executes all integer instructions IU2 executes all integer instructions except multiply and divide instructions The ability to execute several instructions in parallel and the use of simple instructions with rapid execution time...

Page 43: ...s The L2 cache interface is not implemented in the MPC740 For information about the L2 cache implementation see Chapter 9 L2 Cache Interface Operation The MPC750 has a 32 bit address bus and a 64 bit data bus Multiple devices compete for system resources through a central external arbiter The MPC750 s three state cache coherency protocol MEl supports the exclusive modified and invalid states a com...

Page 44: ... Station II Reservation Station I Reservation Station IReservation Station GPR File 2 Entry FPR File Rename Buffers Rename Buffers 6 6 ISystem Register 1 2 load Store Unit I I I I i Floating Point IntegerUnitt IntegerUnit 2 Unit Unit I iJ I tEA Calculation II CR I Store Queue I FPSCR I I t I I I 32 Bit 32 Bit 1 1 PA EA 1 c f Completion Unit SOx Bus Interface Unit I Data MMU I 64 Bit Instruction Fe...

Page 45: ...e sooner than it can be made available from the instruction cache Typically if a fetch access hits the BTIC it provides the first two instructions in the target stream 512 entry branch history table BHT with two bits per entry for four levels of prediction not taken strongly not taken taken strongly taken Branch instructions that do not update the count register CTR or link register LR are removed...

Page 46: ...ave been completed the instruction has finished execution and no exceptions are pending Guarantees sequential programming model precise exception model Monitors all dispatched instructions and retires them in order Tracks unresolved branches and flushes instructions from the mispredicted branch Retires as many as two instructions per clock Separate on chip instruction and data caches Harvard archi...

Page 47: ...rite through cacheable noncacheable and coherency enforced coherency not enforced on a page or block basis Separate IBATs and DBATs four each also defined as SPRs Separate instruction and data translation lookaside buffers TLBs Both TLBs are 128 entry two way set associative and use LRU replacement algorithm TLBs are hardware reloadable that is the page table search is performed in hardware Separa...

Page 48: ...functional units are disabled after which external system logic may disable the PLL and SYSCLK Thermal management facility provides software controllable thermal management Thermal management is performed through the use of three supervisor level registers and an MPC750 specific thermal management exception Instruction cache throttling provides control of instruction fetching to limit power consum...

Page 49: ...s many instructions as there were vacancies in the IQ in the previous clock cycle All instructions except branch instructions are dispatched to their respective execution units from the bottom two positions in the instruction queue IQO and IQl at a maximum rate of two instructions per cycle Reservation stations are provided for the lUI IU2 FPU LSU and SRU The dispatch unit checks for source and de...

Page 50: ...h target instructions typically in pairs When an instruction fetch hits in the BTIC the instructions arrive in the instruction queue in the next clock cycle a clock cycle sooner than they would arrive from the instruction cache Additional instructions arrive from the instruction cache in the next clock cycle The BTIC reduces the number of missed opportunities to dispatch instructions and gives the...

Page 51: ...r instruction except multiplication and division instructions Each IU has a single entry reservation station that can receive instructions from the dispatch unit and operands from the GPRs or the rename buffers Each IU consists of three single cycle subunits a fast adder comparator a subunit for logical operations and a subunit for performing rotates shifts and count leading zero operations These ...

Page 52: ...er however some memory accesses can occur out of order Synchronizing instructions can be used to enforce strict ordering When there are no data dependencies and the guarded bit for the page or block is cleared a maximum of one out of order cacheable load operation can execute per cycle with a two cycle total latency on a cache hit Data returned from the cache is held in a rename register until the...

Page 53: ...nslated and therefore considered both logical and physical are directed to the on chip caches where they form the index into the eight way set associative tag array After translating the address the MMU passes the higher order physical address bits to the cache and the cache lookup completes For caching inhibited accesses or accesses that miss in the cache the untranslated lower order address bits...

Page 54: ...cache organization is shown in Figure 1 2 128 Sets I I i f f Block 0 Address Tag 0 t State Words 0 7 Block 1 Address Tag 1 I State Words 0 7 Block 2 Address Tag 2 t State Words 0 7 Block 3 Address Tag 3 t State Words 0 7 Block 4 Address Tag 4 f State Words 0 7 Block 5 Address Tag 5 I State Words 0 7 Block 6 Address Tag 6 State Words 0 7 Block 7 Address Tag 7 State Words 0 7 1 8 Words Block I I Fig...

Page 55: ...ports a single bank of up to 1 Mbyte of synchronous SRAMs The L2 cache normally operates in write back mode and supports system cache coherency through snooping Depending on its size the L2 cache is organized into 64 or 128 byte lines which in tum are subdivided into 32 byte sectors blocks the unit at which cache coherency is maintained The L2 cache controller contains the L2 cache control registe...

Page 56: ...vity for example when a snooped read access hits a modified block in the cache The broadcast of some address only operations is controlled through HIDO ABE I O accesses use the same protocol as memory accesses Access to the system interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership This arbitration mechanism is flexible allowing the MPC7...

Page 57: ...k ratios 1 2 7 Signals The MPC750 s signals are grouped as follows Address arbitration signals The MPC750 uses these signals to arbitrate for address bus mastership Address start signals These signals indicate that a bus master has begun a transaction on the address bus Address transfer signals These signals include the address bus and address parity signals They are used to transfer the address a...

Page 58: ...status control signals These signals are used to set the reservation coherency bit enable the time base and other functions Miscellaneous signals These signals are used in conjunction with such resources as secondary caches and the time base facility JTAG COP interface signals The common on chip processor COP unit provides a serial interface to the system for performing board level boundary scan i...

Page 59: ...TBST 1 1 TSIZ 0 2 1 SMI 3 GBL 1 MCP 1 SRESET Interrupts WT 1 1 HRESET Resets CI 1 MPC750 1 1 CKSTP IN 1 CKSTP OUT AACK 1 ARTRY 1 RSRV 1 1 TBEN DBG 1 TLBISYNC Processor DBWO 1 Status 1 1 QREQ Control DBB 1 QACK 1 D 0 63 64 1 SYSCLK DP Q 7 8 4 PLL CFG 0 3 Clock DBDIS CLK OUT Control 1 1 fA 1 JTAG COP 5 Test DRTRY 1 Factory Test Interface TEA 3 1 I I I VDD VDD I O AVDD Figure 1 4 MPC750 Microprocesso...

Page 60: ...Optimized with Enhanced RISC architecture The PowerPC architecture shares the benefits of the POWER architecture optimized for single chip implementations The PowerPC architecture design facilitates parallel instruction execution and is scalable to take advantage of future technological gains This section describes the PowerPC architecture in general and specific details about the implementation o...

Page 61: ... this section is described more fully in Chapter 6 Instruction Timing Power management Section 1 10 Power Management describes how the power management can be used to reduce power consumption when the processor or portions of it are idle The information in this section is described more fully in Chapter 10 Power and Thermal Management Thermal management Section 1 11 Thermal Management describes ho...

Page 62: ...PC Microprocessor Family The Programming Environments Specific features of the MPC750 are listed in Section 1 2 MPC750 Microprocessor Features 1 4 PowerPC Registers and Programming Model The PowerPC architecture defines register to register operations for most computational instructions Source operands for these instructions are accessed from the registers or are provided as immediate values embed...

Page 63: ... supervisor level The numbers to the right of the SPRs indicate the number that is used in the syntax of the instruction operands to access the register For more information see Chapter 2 MPC750 Processor Programming Model 1 22 MPC750 RISC Microprocessor User s Manual ...

Page 64: ...PMC2 SPR 938 FPR31 I DAR ISPR 19 SPR26 SPRGI SPR 273 UPMC3 SPR 941 DSISR SRRI SPR27 Condition SPRG2 SPR 274 UPMC4 SPR 942 Register I ISPR18 SPRG3 SPR 275 DSISR Sampled Instruction I CR I Address 1 Miscellaneous Registers I USIA I SPR 939 Floating Point External Access Time Base Decrementer Status and Monitor Control1 Control Register Register For Writing I DEC ISPR22 I I O SPR282 EESPR284 UMMCRO S...

Page 65: ...SRs define the 4 Gbyte space as sixteen 256 Mbyte SR15 segments The MPC750 implements segment registers as two arrays a main array for data accesses and a shadow array for instruction accesses see Figure 1 1 Loading a segment entry with the Move to Segment Register mtsr instruction loads both arrays The mfsr instruction reads the master register shown as part of the data MMU in Figure 1 1 The OEA ...

Page 66: ...ut Word Indexed ecowx instructions PVR Supervisor The processor version register PVR is a read only register that identifies the processor SDR1 Supervisor SDR1 specifies the page table format used in virtual to physical page address translation SRRO Supervisor The machine status save restore register 0 SRRO saves the address used for restarting an interrupted program when a Return from Interrupt r...

Page 67: ...isor The performance monitor counter registers PMC1 PMG4 are used to count specified PMC4 events UPMC1 UPMC4 provide user level read access to these registers SIA Supervisor The sampled instruction address register SIA holds the EA of an instruction executing at or around the time the processor signals the performance monitor interrupt condition The USIA register provides user level read access to...

Page 68: ...rol instructions Load store instructions These include integer and floating point load and store instructions Integer load and store instructions Integer load and store multiple instructions Floating point load and store Primitives used to construct atomic memory operations lwarx and stwcx instructions Flow control instructions These include branching instructions condition register logical instru...

Page 69: ...y the same or another memory location the memory contents must be loaded into a register modified and then written back to the target location with distinct instructions PowerPC processors follow the program flow when they are in the normal execution state However the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event Either kind of exce...

Page 70: ...management instructions a programmer can use to affect cache contents 1 6 2 MPC750 Microprocessor Cache Implementation The MPC750 cache implementation is described in Section 1 2 4 On Chip Instruction and Data Caches and Section 1 2 5 L2 Cache Implementation Not Supported in the MPC740 The BPU also contains a 64 entry BTIC that provides immediate access to cached target instructions For more infor...

Page 71: ...tially guarantees that exceptions are recoverable When an exception is taken information about the processor state before the exception was taken is saved in SRRO and SRRI Exception handlers should save the information stored in SRRO and SRRI early to prevent the program state from being lost due to a system reset and machine check exception or to an instruction caused exception in the exception h...

Page 72: ...ine check system reset Asynchronous maskable Precise External decrementer system management performance monitor and thermal management interrupts Synchronous Precise Instruction caused exceptions Although exceptions have other characteristics such as priority and recoverability Table 1 4 describes categories of exceptions the MPC750 handles uniquely Table 1 4 includes no synchronous imprecise exce...

Page 73: ... definition isync does not cause a trace exception Reserved OOEOO The MPC750 does not generate an exception to this vector Other PowerPC processors may use this vector for floating point assist exceptions Reserved OOE1O oOEFF Performance monitorl OOFOO The limit specified in a PMC register is reached and MMCRO ENINT 1 Instruction address 01300 IABR 0 29 matches EA 0 29 of the next instruction to c...

Page 74: ...ams larger than the size of physical memory demand paged implies that individual pages are loaded into physical memory from system memory only when they are first accessed by an executing program The hashed page table is a variable sized data structure that defines the mapping between virtual page numbers and physical page numbers The page table size is a power of 2 and its starting address is a m...

Page 75: ...ers are provided to allow operations to post execution results for use by subsequent instructions without committing them to the architected FPRs and GPRs As shown in Figure 1 6 the common pipeline of the MPC750 has four stages through which all instructions must pass fetch decode dispatch execute and complete write back Some instructions occupy multiple stages simultaneously and some individual e...

Page 76: ...ute pipeline stage each execution unit that has an executable instruction executes the selected instruction perhaps over multiple cycles writes the instruction s result into the appropriate rename register and notifies the completion stage that the instruction has finished execution In the case ofan internal exception the execution unit reports the exception to the completion pipeline stage and ex...

Page 77: ...wer state The MPC750 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input SYSCLK so a transition to the full power state takes only a few processor clock cycles Nap The nap mode further reduces power consumption by disabling bus snooping leaving only the time base register and the PLL in a powered state The MPC750 returns to the full power state upo...

Page 78: ... TAU does the following Compares the junction temperature against user programmable thresholds Generates a thermal management interrupt if the temperature crosses the threshold Enables the user to estimate the junction temperature by way of a software successive approximation routine The TAU is controlled through the privileged mtspr mfspr instructions to the three SPRs provided for configuring an...

Page 79: ...isters and Programming Model Performance monitor control registers MMCRO or MMCR1 can be used to specify which events are to be counted and the conditions for which a performance monitoring interrupt is taken Additionally the sampled instruction address register SIA USIA holds the address of the first instruction to complete after the counter overflowed Attempting to write to a user read only perf...

Page 80: ...PowerPC architecture user instruction set architecture UISA virtual environment architecture YEA and operating environment architecture OEA The PowerPC architecture defines register to register operations for all computational instructions Source data for these instructions are accessed from the on chip registers or are provided as immediate values embedded in the opcode The three register instruc...

Page 81: ... ISPR19 SPR26 SPRGI SPR 273 UPMC3 SPR 941 DSISR SRRI SPR 27 Condition SPRG2 SPR 274 UPMC4 SPR 942 Register IDSISR SPR 18 SPRG3 SPR 275 Sampled Instruction I CR I Address 1 Miscellaneous Registers I USIA I SPR 939 FlOating Point External Address Time Base Decrementer Status and Monitor Control1 Control Register Register For Writing I DEC ISPR 22 I ISPR 282 I I EAR SPR284 UMMCRO SPR 936 FPSCR TBU SP...

Page 82: ...hapter 2 PowerPC Register Set ofThe Programming Environments Manual Condition register CR The 32 bit CR consists of eight 4 bit fields CRO CR7 that reflect results of certain arithmetic operations and provide a mechanism for testing and branching See Condition Register CR in Chapter 2 PowerPC Register Set of The Programming Environments Manual Floating point status and control register FPSCR The F...

Page 83: ...ng and other operating system functions The OEA defines the following supervisor level registers for 32 bit implementations Configuration registers Machine state register MSR The MSR defines the state of the processor The MSR can be modified by the Move to Machine State Register mtmsr System Call sc and Return from Exception rfi instructions It can be read by the Move from Machine State Register m...

Page 84: ...apter 2 PowerPC Register Set of The Programming Environments Manual Because BAT upper and lower words are loaded separately software must ensure that BAT translations are correct during the time that both BAT entries are being loaded The MPC750 implements the G bit in the IBAT registers however attempting to execute code from an IBAT area with G 1 causes an lSI exception This complies with the rev...

Page 85: ...ter is used to save machine status on exceptions and to restore machine status when rfi executes See Machine Status Save Restore Register 1 SRRl in Chapter 2 PowerPC Register Set of The Programming Environments Manual for more information Implementation Note When a machine check exception occurs the MPC750 sets one or more error bits in SRRI Table 2 2 describes SRRI bits the MPC750 implements that...

Page 86: ...ecific SPRs Those incorporated in the MPC750 are described as follows Note that in the MPC750 these registers are all supervisor level registers Instruction address breakpoint register IABR This register can be used to cause a breakpoint exception if a specified instruction address is encountered Hardware implementation dependent register 0 HIDO This register controls various functions such as ena...

Page 87: ... degrees of action in lowering the junction temperature The TAU can be also operated in a single threshold mode in which the thermal sensor output is compared to only one threshold in either THRMI or THRM2 THRM3 is used to enable the thermal management assist unit TAU and to control the comparator output sample time Note that while it is not guaranteed that the implementation of MPC750 specific re...

Page 88: ...this bit is to mask out further machine check exceptions caused by assertion of Mep similar to how MSR EE can mask external interrupts 0 Masks Mep Asserting MCP does not generate a machine check exception or a checkstop 1 Asserting Mep causes checkstop if MSR ME 0 or a machine check exception if ME 1 1 DBP Enable disable 60x bus address and data parity generation 0 If the system does not use addre...

Page 89: ... while this bit is set QREQ is asserted to indicate that the processor is ready to enter sleep mode If the system logic determines that the processor may enter sleep mode the quiesce acknowledge signal QACK is asserted back to the processor Once QACK assertion is detected the processor enters sleep mode after several processor clocks At this point the system logic may turn off the Pll by first con...

Page 90: ... instruction cache must be enabled for the invalidation to occur 1 An invalidate operation is issued that marks the state of each instruction cache block as invalid without writing back modified cache blocks to memory Cache access is blocked during this time Bus accesses to the cache are signaled as a miss during invalidate all operations Setting ICFI clears all the valid bits of the blocks and th...

Page 91: ... the BTIC behaves as if it were empty New entries cannot be added until the BTIC is enabled 27 Not used Defined as FBIOB on earlier 603 type processors 28 ABE Address broadcast enable controls whether certain address only operations such as cache operations eieio and sync are broadcast on the 60x bus 0 Address only operations affect only local L1 and L2 caches and are not broadcast 1 Address only ...

Page 92: ...implementation dependent register 1 HID 1 reflects the state of the PLL_CFG 0 3 signals The HIDI bits are shown in Figure 2 4 o Reserved o 1 234 Figure 2 4 Hardware Implementation Dependent Register 1 HID1 The HIDl bits are described in Table 2 6 Table 2 6 HID1 Bit Functions Bit s Name Description 0 PCO PLL configuration bit 0 read only 1 PC1 PLL configuration bit 1 read only 2 PC2 PLL configurati...

Page 93: ...ot change its contents The bits of the MMCRO register are described in Table 2 7 Table 2 7 MMCRO Bit Settings Bit Name Description 0 DIS Disables counting unconditionally 0 The values of the PMCn counters can be changed by hardware 1 The values of the PMCn counters cannot be changed by hardware 1 DP Disables counting while in supervisor mode 0 The PMCn counters can be changed by hardware 1 If the ...

Page 94: ...Do not allow interrupt signal if chosen bit transitions 1 Signal interrupt if chosen bit transitions Software is responsible for setting and clearing INTONBITTRANS 10 15 THRESHOLD Threshold value The MPC750 supports all 6 bits allowing threshold values from 0 63 The intent of the THRESHOLD support is to characterize L1 data cache misses 16 PMCllNTCONTROL Enables interrupt signaling due to PMCI cou...

Page 95: ...electable See Table 2 13 for defined selections 10 31 Reserved MMCRI can be accessed with mtspr and mfspr using SPR 956 User level software can read the contents of MMCRI by issuing an mfspr instruction to UMMCRI described in Section 2 1 2 4 4 User Monitor Mode Control Register 1 UMMCRl 2 1 2 4 4 User Monitor Mode Control Register 1 UMMCR1 The contents of MMCRI are reflected to UMMCRl which can be...

Page 96: ...ed beginning when MMCRO is set until either MMCRO is reset or a performance monitor interrupt is generated Table 2 10 lists the selectable events and their encodings Table 2 10 PMC1 Events MMCRO 19 25 Select Encodings Encoding Description 0000000 Register holds current value 0000001 Number of processor cycles 0000010 Number of completed instructions Does not include folded branches 0000011 Number ...

Page 97: ...reshold value 001011 Number of branches that are unresolved when processed 001100 Number of cycles the dispatcher stalls due to a second unresolved branch in the instruction stream All others Reserved May be used in a later revision Bits MMCR1 0 4 specify events associated with PMC3 as shown in Table 2 12 Table 2 12 PMC3 Events MMCR1 0 41 Select Encodings Encoding Description 00000 Register holds ...

Page 98: ...ng folded branches 00011 Number of transitions from 0 to 1 of specified bits in the time base lower register Bits are specified through RTCSELECT MMRCO 7 8 0 47 1 51 2 55 3 63 00100 Number of instructions dispatched 0 1 or 2 per cycle 00101 Number of L2 castouts 00110 Number of cycles spent performing tables searches for DTLB accesses 00111 Reserved May be used in a later revision 01000 Number of ...

Page 99: ...egisters SIA If the performance monitor interrupt is triggered by a threshold event the SIA contains the exact instruction called the sampled instruction that caused the counter to overflow If the performance monitor interrupt was caused by something besides a threshold event the SIA contains the address of the last instruction completed during that cycle SIA can be accessed with the mtspr and mfs...

Page 100: ...its Name Description 0 22 Reserved 23 30 FI Instruction forwarding interval expressed in processor clocks OxOO oclock cycle Ox01 1 clock cycle OxFF 255 clock cycles 31 E Cache throttling enable 0 Disable instruction cache throttling 1 Enable instruction cache throttling Instruction cache throttling is enabled by setting ICTC E and writing the instruction forwarding interval into ICTC FI Enabling d...

Page 101: ...and each bit represents 1 C Note that this is not the resolution of the thermal sensor 9 28 Reserved System software should clear these bits when writing to the THRMn SPRs 29 TID Thermal management interrupt direction bit Selects the result of the temperature comparison to set TIN and to assert a thermal management interrupt if TIE is set If TID is cleared TIN is set and an interrupt occurs if the...

Page 102: ...a x 1 The junction temperature is greater than the threshold and as a result the thermal management interrupt is generated if TIE 1 a 1 1 x 1 The junction temperature is greater than the threshold and as a result the thermal management interrupt is not generated for TIE 1 1 1 1 x 1 The junction temperature is less than the threshold and as a result the thermal management interrupt is generated ifT...

Page 103: ...rval of 20 microseconds 31 E Enables the thermal sensor compare operation if either THRM1 V or THRM2 V is set The THRM registers can be accessed with the mtspr and mfspr instructions using the following SPR numbers THRM1 is SPR 1020 THRM2 is SPR 1021 THRM3 is SPR 1022 2 1 5 L2 Cache Control Register L2CR The L2 cache control register shown in Figure 2 12 is a supervisor level implementation specif...

Page 104: ...the 60x bus interface 000 L2 clock and DLL disabled 001 1 010 1 5 011 Reserved 100 2 101 2 5 110 3 111 Reserved 7 8 L2RAM L2 RAM type Configures the L2 RAM interface for the type of synchronous SRAMs used Flow through register buffer synchronous burst SRAMs that clock addresses in and flow data out Pipelined register register synchronous burst SRAMs that clock addresses in and clock data out Late ...

Page 105: ... set according to the SRAM s input hold time requirements for which late write SRAMs usually differ from flow through or burst SRAMs 00 0 5 nS 01 1 0 nS 1x Reserved 16 L2SL L2 DLL slow Setting L2SL increases the delay of each tap of the DLL delay line It is intended to increase the delay through the DLL to accommodate slower L2 RAM bus frequencies Generally L2SL should be set if the L2 RAM interfa...

Page 106: ...on flag Cleared DAR OxOOOO_OOOO SDR1 OxOOOO_OOOO DEC OxFFFFJFFF SIA OxOOOO_OOOO DSISR OxOOOO_OOOO SPRGO SPGR3 OxOOOO_OOOO EAR OxOOOO_OOOO SRs Undefined FPR Undefined SRRO OxOOOO_OOOO FPSCR OxOOOO_OOOO SRR1 OxOOOO_OOOO GPR Undefined TBU andTBL OxOOOO_OOOO HIDO OxOOOO_OOOO THRM1 THRM3 OxOOOO_OOOO HID1 OxOOOO_OOOO TLB Undefined IABR OxOOOO_OOOO Breakpoint is disabled UMMCRn OxOOOO_OOOO ICTC OxOOOO_OO...

Page 107: ... precision must be done explicitly by software while conversion from single to double precision is done implicitly by the processor All PowerPC implementations provide the equivalent of the following execution models to ensure that identical results are obtained The definition of the arithmetic instructions for infinities denormalized numbers and NaNs follow conventions described in the following ...

Page 108: ...invokes an alignment exception and it is left up to software to break up the offending storage access operation appropriately In addition some non double word aligned memory accesses suffer performance degradation as compared to an aligned access of the same type In general floating point word accesses should always be word aligned and floating point double word accesses should always be double wo...

Page 109: ... or zero Normalize A Zero A Double denormalized Normalized or zero Single denormalized Normalized or zero Normalize B Zero B Double denormalized Normalized or zero Normalized or zero Single denormalized Normalize C Zero C Double denormalized Single QNaN Don t care Don t care QNaN1 QNaN1 Single SNaN Double QNaN Double SNaN Don t care Single QNaN Don t care QNaN1 QNaN1 Single SNaN Double QNaN Double...

Page 110: ...These include arithmetic and logical instructions For more information see Section 2 3 4 1 Integer Instructions Floating point instructions These include floating point arithmetic instructions as well as instructions that affect the floating point status and control register FPSCR For more information see Section 2 3 4 2 Floating Point Instructions Load and store instructions These include integer...

Page 111: ...and a set of 32 general purpose registers GPRs It also provides for word and double word operand loads and stores between memory and a set of 32 floating point registers FPRs Arithmetic and logical instructions do not read or modify memory To use the contents of a memory location in a computation and then modify the same or another memory location the memory contents must be loaded into a register...

Page 112: ... between execution attempts in the same implementation 2 3 1 2 Defined Instruction Class Defined instructions are guaranteed to be supported in all PowerPC implementations except as stated in the instruction descriptions in Chapter 8 Instruction Set in The Programming Environments Manual The MPC750 provides hardware support for all instructions defined for 32 bit implementations It does not suppor...

Page 113: ...described in Section 2 3 1 4 Reserved Instruction Class The MPC750 invokes the system illegal instruction error handler a program exception when it detects any instruction from this class or any instructions defined only for 64 bit implementations See Section 4 5 7 Program Exception Ox00700 for additional information about illegal and invalid instruction exceptions Except for an instruction consis...

Page 114: ... and little endian byte ordering The default byte and bit ordering is big endian See Byte Ordering in Chapter 3 Operand Conventions of The Programming Environments Manual for more information about big and little endian byte ordering The operand of a single register memory access instruction has a natural alignment boundary equal to the operand length In other words the natural address of an opera...

Page 115: ... prior memory access instruction causes direct store error exceptions the results are guaranteed to be determined before this instruction is executed Previous instructions complete execution in the context privilege protection and address translation under which they were issued The instructions following the sc or rfi instruction execute in the context established by these instructions 2 3 2 4 2 ...

Page 116: ...o op An attempt to access memory that is not available page fault causes the lSI or DSI exception handler to be invoked The execution of an sc instruction invokes the system call exception handler that permits a program to request the system to perform a service The execution of a trap instruction invokes the program exception trap handler The execution of an instruction that causes a floating poi...

Page 117: ... the integer arithmetic instructions for the PowerPC processors Table 2 22 Integer Arithmetic Instructions Name Mnemonic Syntax Add Immediate addl rD rA SIMM Add Immediate Shifted addis rD rA SIMM Add add add addo addo rD rA rB Subtract From subf subf subfo subfo rD rA rB Add Immediate Carrying addie rD rA SIMM Add Immediate Carrying and Record addle rD rA SIMM Subtract from Immediate Carrying sub...

Page 118: ...uction Timing describes how the MPC750 handles CR dependencies The summary overflow bit SO and overflow bit OV in the integer exception register are set to reflect an overflow condition of a 32 bit result This can happen only when OE 1 2 3 4 1 2 Integer Compare Instructions The integer compare instructions algebraically or logically compare the contents of register rA with either the zero extended...

Page 119: ...ction except for pending trace or breakpoint exceptions OR Immediate Shifted oris rA rS UIMM XOR Immediate xori rA rS UIMM XOR Immediate Shifted xoris rA rS UIMM AND and and rA rS rB OR or or rA rS rB XOR xor xor rA rS rB NAND nand nand rA rS rB NOR nor nor rA rS rB Equivalent eqv eqv rA rS rB AND with Complement andc andc rA rS rB OR with Complement orc orc rA rS rB Extend Sign Byte extsb extsb r...

Page 120: ...and shift values for certain rotate instructions Simplified mnemonics shown in Appendix F Simplified Mnemonics in The Programming Environments Manual are provided to make coding of such shifts simpler and easier to understand Multiple precision shifts can be programmed as shown in Appendix C Multiple Precision Shifts in The Programming Environments Manual The integer shift instructions are summari...

Page 121: ...v fdiv frD frA frB Floating Divide Single fdlvs fdlvs frD frA frS Floating Reciprocal Estimate Single 1 tres tres frD frB Floating Reciprocal Square Root Estimate 1 frsqrte frsqrte frD frB Floating Select 1 tsel frD frA frC frB 1The fsel instruction is optional in the PowerPC architecture All single precision arithmetic instructions are performed using a double precision format The floating point ...

Page 122: ...tructions convert a 64 bit double precision floating point number to a 32 bit signed integer number Examples of uses of these instructions to perform various conversions can be found in Appendix D Floating Point Models in The Programming Environments Manual Table 2 29 Floating Point Rounding and Conversion Instructions Name Mnemonic Syntax Floating Round to Single frsp frsp frD frB Floating Conver...

Page 123: ...s mffs frO Move to Condition Register from FPSCR mcrls crlO crlS Move to FPSCR Field Immediate mtfsfi mtfsti crlO IMM Move to FPSCR Fields mtfsf mtfst FM frB Move to FPSCR Bit a mtfsbO mtfsbO crbO Move to FPSCR Bit 1 mtfsb1 mtfsb1 crbO Implementation Note The PowerPC architecture states that in some implementations the Move to FPSCR Fields mtfsf instruction may perform more slowly when only some o...

Page 124: ...he accesses meet the criteria described in Section 6 4 7 Integer Store Gathering Note that the PowerPC architecture requires load store multiple instruction accesses to be aligned At a minimum additional cache access cycles are required Although many unaligned memory accesses are supported in hardware the frequent use of them is discouraged since they can compromise the overall performance of the ...

Page 125: ...essed by the EA effective address is loaded into rD Many integer load instructions have an update form in which rA is updated with the generated effective address For these forms if rA F 0 and rA F rD otherwise invalid the EA is placed into rA and the memory element byte half word word or double word addressed by the EA is loaded into rD Note that the PowerPC architecture defines load with update ...

Page 126: ...and Zero 1hz rD d rA Load Half Word and Zero Indexed Ihzx rD rA rB Load Half Word and Zero with Update Ihzu rD d rA Load Half Word and Zero with Update Indexed Ihzux rD rA rB Load Half Word Algebraic Iha rD d rA Load Half Word Algebraic Indexed Ihax rD rA rB Load Half Word Algebraic with Update Ihau rD d rA Load Half Word Algebraic with Update Indexed Ihaux rD rA rB Load Word and Zero Iwz rD d rA ...

Page 127: ... gathering for write through accesses to nonguarded space or to cache inhibited stores to nonguarded space if the stores are 4 bytes and they are word aligned These stores are combined in the load store unit LSU to form a double word and are sent out on the 60x bus as a single beat operation However stores can be gathered only if the successive stores that meet the criteria are queued and pending ...

Page 128: ... The load multiple and store multiple instructions may have operands that require memory accesses crossing a 4 Kbyte page boundary As a result these instructions may be interrupted by a DSI exception associated with the address translation of the second page Implementation Notes The following describes the MPC750 implementation of the load store multiple instruction For load store string operation...

Page 129: ... Indexed stswx rS rA rS Load string and store string instructions may involve operands that are not word aligned As described in Section 4 5 6 Alignment Exception Ox00600 a misaligned string operation suffers a performance penalty compared to an aligned operation ofthe same type A non word aligned string operation that crosses a 4 Kbyte boundary or a word aligned string operation that crosses a 25...

Page 130: ... stfdx stfdux are invalid when the Rc bit is one In the MPC750 executing one of these invalid instruction forms causes CRO to be set to an undefined value The PowerPC architecture defines a load with update instruction with rA 0 as an invalid form Table 2 38 summarizes the floating point load instructions Table 2 38 Floating Point Load Instructions Name Mnemonic Syntax Load Floating Point Single I...

Page 131: ... frS r B Store Floating Point as Integer Word Indexed 1 stfiwx frS rB 1The stfiwx instruction is optional to the PowerPC architecture Some floating point store instructions require conversions in the LSD Table 2 40 shows conversions the LSD makes when executing a Store Floating Point Single instruction Table 2 40 Store Floating Point Single Behavior FPR Precision Data Type Action Single Normalized...

Page 132: ... of a store floating point double stfd stfdu stfdx stfdux instruction can require internal shifting of the mantissa This case occurs when the operand of a store floating point double instruction is a denormalized single precision value The value could be the result of a load floating point single instruction a single precision arithmetic instruction or a floating round to single precision instruct...

Page 133: ...resolution of the condition registers bits 2 3 4 4 2 Branch Instructions Table 2 42 lists the branch instructions provided by the PowerPC processors To simplify assembly language programming a set of simplified mnemonics and symbols is provided for the most frequently used forms of branch conditional compare trap rotate and shift and certain other instructions See Appendix F Simplified Mnemonics i...

Page 134: ...ap instruction are met the system trap type program exception is taken For more information see Section 4 5 7 Program Exception Ox00700 If the tested conditions are not met instruction execution continues normally Table 2 44 Trap Instructions Name Mnemonic Syntax Trap Word Immediate twi TO rA SIMM Trap Word tw TO rA rB See Appendix F Simplified Mnemonics in The Programming Environments Manual for ...

Page 135: ...indicates that in some implementations the Move to Condition Register Fields mtcrO instruction may perform more slowly when only a portion ofthe fields are updated as opposed to all ofthe fields The condition register access latency for the MPC750 is the same in both cases 2 3 4 6 2 Move to from Special Purpose Register Instructions UISA Table 2 47 lists the mtspr and mfspr instructions Table 2 47...

Page 136: ...0 10000 10010 Supervisor OEA Both IBAT2l 533 10000 10101 Supervisor OEA Both IBAT2U 532 10000 10100 Supervisor OEA Both IBAT3l 535 10000 10111 Supervisor OEA Both IBAT3U 534 10000 10110 Supervisor OEA Both lR 8 00000 01000 User UISA Both PVR 287 01000 11111 Supervisor OEA mfspr SDR1 25 00000 11001 Supervisor OEA Both SPRGO 272 01000 10000 Supervisor OEA Both SPRG1 273 01000 10001 Supervisor OEA Bo...

Page 137: ...d in user mode using either the mftb or mtspr instruction and specifying TBR 268 for TBl and SPR 269 for TBU Encodings for the MPC750 specific SPRs are listed in Table 2 49 Table 2 49 SPR Encodings for MPC750 Defined Registers mfspr Register SPR1 Name Access mfspr mtspr Decimal spr 5 9 spr 0 4 DABR 1013 11111 10101 User Both HIDO 1008 11111 10000 Supervisor Both HIDI 1009 11111 10001 Supervisor Bo...

Page 138: ...er 3 Ll Instruction and Data Cache Operation for additional information about these instructions and about related aspects of memory synchronization See Table 2 50 for a summary Table 2 50 Memory Synchronization Instructions UISA Name Mnemonic Syntax Implementation Notes Load Word Iwarx rO rA rB Programmers can use Iwarx with stwcx to emulate common semaphore and Reserve operations such as test an...

Page 139: ...mory synchronization eieio and isync instructions In the PowerPC architecture the Rc bit must be zero for most load and store instructions IfRc is set the instruction form is invalid for sync and lwarx instructions If the MPC750 encounters one of these invalid instruction forms it sets CRO to an undefined value 2 3 5 PowerPC VEA Instructions The PowerPC virtual environment architecture VEA describ...

Page 140: ...ve from Time Base Upper mftbu instructions As a 32 bit PowerPC implementation the MPC750 can access TBU and TBL only separately whereas 64 bit implementations can access the entire TB register at once The time base counter is clocked at a frequency that is one fourth that of the bus clock Counting is enabled by assertion of the time base enable TBE input signal 2 3 5 2 Memory Synchronization Instr...

Page 141: ...plete Any instruction after an isync sees all effects of prior instructions 2 3 5 3 Memory Control Instructions VEA Memory control instructions can be classified as follows Cache management instructions user level and supervisor level Segment register manipulation instructions OEA Translation lookaside buffer management instructions OEA This section describes the user level cache management instru...

Page 142: ...violation The page is mapped cache inhibited G 1 guarded or T 1 The cache is locked or disabled HIDO NOOPTI 1 Otherwise if no data is in the cache location the MPC750 requests a cache line fill with intent to modify Data brought into the cache is validated as if it were a load instruction The memory reference of a debt sets the reference bit Data Cache Block debtst rA rB This instruction behaves l...

Page 143: ...s a virtual lookup into the instruction cache index Block Invalidate only The address is not translated so it cannot cause an exception All ways of a selected set are invalidated regardless of whether the cache is disabled or locked The MPC750 never broadcasts iebi onto the 60x bus Note 1 A program that uses debt and dcbtst instructions improperly performs less efficiently To improve performance H...

Page 144: ...ection describes the instructions provided by the OEA 2 3 6 1 System Linkage Instructions OEA This section describes the system linkage instructions see Table 2 55 The user level sc instruction lets a user program call on the system to perform a service and causes the processor to take a system call exception The supervisor level rfi instruction is used for returning from an exception handler Tabl...

Page 145: ...supervisor level memory control instructions Section 2 3 5 3 Memory Control Instructions VEA describes user level memory control instructions 2 3 6 3 1 Supervisor Level Cache Management Instruction OEA Table 2 58 lists the only supervisor level cache management instruction Table 2 58 Supervisor Level Cache Management Instruction Name Mnemonic Syntax Implementation Notes Oata dcbi rA rB The EA is c...

Page 146: ...rticular access These segment descriptors and PTEs reside in segment registers and page tables in memory respectively See Chapter 7 Memory Management for more information about TLB operations Table 2 60 summarizes the operation of the TLB instructions in the MPC750 Table 2 60 Translation Lookaside Buffer Management Instruction Name Mnemonic Syntax Implementation Notes TLB tlbie rB Invalidates both...

Page 147: ... set of alternative mnemonics is provided for some frequently used operations such as no op load immediate load address move register and complement register Programs written to be portable across the various assemblers for the PowerPC architecture should not assume the existence of mnemonics not described in this document For a complete list of simplified mnemonics see Appendix F Simplified Mnemo...

Page 148: ...hes and function as bus masters requiring cache coherency The MPC750 cache implementation has the following characteristics There are two separate 32 Kbyte instruction and data caches Harvard architecture Both instruction and data caches are eight way set associative The caches implement a pseudo least recently used PLRU replacement algorithm within each set The cache directories are physically ad...

Page 149: ...e to cache fill latency The instruction and data caches are integrated into the MPC750 as shown in Figure 3 1 Instruction Unit nstructions 0 127 I Cache 32 Kbyte 8 Way Set Associative Instructions 0 63 EA Effective Address PA Physical Address EA 20 26 PA 0 31 Load Store Unit LSU Data 0 63 D Cache 32 Kbyte 8 Way Set Associative Data 0 63 _ L ____ _ _ _ _ _ _ __ MMU L2 BIU MPC750 only 60x BIU Figure...

Page 150: ...h block consists of 32 bytes two state bits and an address tag Note that in the PowerPC architecture the term cache block or simply block when used in the context of cache implementations refers to the unit of memory at which coherency is maintained For the MPC750 this is the eight word cache line This value may be different for other PowerPC implementations Each cache block contains eight contigu...

Page 151: ...boundaries Also address bits A 20 26 provide the index to select a set and bits A 27 29 select a word within a block The tags consist of bits PA O 19 Address translation occurs in parallel with set selection from A 20 26 and the higher order address bits the tag bits in the cache are physical The instruction cache differs from the data cache in that it does not implement MEl cache coherency protoc...

Page 152: ...herency The primary objective of a coherent memory system is to provide the same image of memory to all devices using the system Coherency allows synchronization and cooperative use of shared resources Otherwise multiple copies of a memory location some containing stale values could exist in a system resulting in errors when the stale values are used Each potential bus master must follow rules for...

Page 153: ... The operating system writes the WIMG bits for each page into the PTEs in system memory as it sets up the page tables When an access requires coherency the processor performing the access must inform the coherency mechanisms throughout the system that the access requires memory coherency The M attribute determines the kind of access performed on the bus global or local Software must exercise care ...

Page 154: ...odified M The addressed cache block is present in the cache and is modified with respect to system memory that is the modified data in the cache block has not been written back to memory The cache block may be present in the MPC750 s L2 cache but it is not present in any other coherent cache Exclusive E The addressed cache block is present in the cache and this cache has exclusive ownership of the...

Page 155: ... write to it without a bus broadcast transaction To maintain the three state coherency all global reads observed on the bus by the MPC750 are snooped as if they were writes causing the MPC750 to flush the cache block write the cache block back to memory and invalidate the cache block if it is modified or simply invalidate the cache block if it is unmodified The exception to this rule occurs when a...

Page 156: ... MPC750 retries the snoop and raises the priority of the castout operation to allow it to go to the bus before the cache block fill Another consideration is page table aliasing If a store hits to a modified cache block but the page table entry is marked write through WIMG lxxx then the page has probably been aliased through another page table entry which is marked write back WIMG Oxxx If this occu...

Page 157: ...the cache tag The cache block is updated during the write through operation but the block remains in the modified state M Note that when WIM bits are changed in the page tables or BAT registers it is critical that the cache contents reflect the new WIM bit settings For example if a block or page that had allowed caching becomes caching inhibited software should ensure that the appropriate cache bl...

Page 158: ...ite through WIMG lxxx stores are performed when they have been successfully presented to the external60x bus 3 3 5 2 Sequential Consistency of Memory Accesses The PowerPC architecture requires that all memory operations executed by a single processor be sequentially consistent with respect to that processor This means that all memory accesses appear to be executed in program order with respect to ...

Page 159: ...able entry is marked caching allowed WIMG xOxx and an Iwarx access misses in the cache then the MPC750 performs a cache block fill If the page is marked caching inhibited WIMG xlxx or the cache is locked and the access misses then the Iwarx instruction appears on the bus as a single beat load All bus operations that are a direct result of either an Iwarx instruction or an stwcx instruction are pla...

Page 160: ...automatically cleared by the microprocessor Software that has this sequence of operations does not need to be changed to run on the MPC750 3 4 1 2 Data Cache Enabling Disabling The data cache may be enabled or disabled by using the data cache enable bit HIDO DCE HIDO DCE is cleared on power up disabling the data cache When the data cache is in the disabled state HIDO DCE 0 the cache tag state bits...

Page 161: ...truction cache Software must use the HIDO instruction cache flash invalidate bit HIDO ICFI if instruction cache invalidation is desired after a soft reset Once HIDO ICFI is set through an mtspr operation the MPC750 automatically clears this bit in the next clock cycle provided that the instruction cache is enabled in the HIDO register Note that some PowerPC microprocessors accomplish instruction c...

Page 162: ...g other caches in the system except to the extent necessary to maintain coherency The MPC750 does not snoop cache control instruction broadcasts except for debz when M 1 The debz instruction is the only cache control instruction that causes a broadcast on the 60x bus when M 1 to maintain coherency All other data cache control instructions debi debf debst and debz are not broadcast unless broadcast...

Page 163: ...maintain coherency The other cache control instructions are not broadcast unless broadcasting is specifically enabled through the HIDO ABE configuration bit The debz instruction executes regardless of whether the cache is locked but if the cache is disabled an alignment exception is generated If the page containing the byte addressed by the EA is caching inhibited or write through then the system ...

Page 164: ...the PowerPC architecture This instruction is treated as a store with respect to address translation and memory protection If the address hits in the cache the cache block is placed in the invalid I state regardless of whether the data is modified Because this instruction may effectively destroy modified data it is privileged that is debi is available to programs at the supervisor privilege level M...

Page 165: ...e the missed data is being accessed on the bus When the load completes the MPC750 then pushes the replaced cache block from the castout buffer to the L2 cache if L2 is enabled or to main memory if L2 is disabled The replacement logic first checks to see if there are any invalid blocks in the set and chooses the lowest order invalid block L O 7 as the replacement target If all eight blocks in the s...

Page 166: ...id L3 valid L4invalid L4 valid L5invalid L5 valid L6invalid L6 valid L7invalid L7 valid Allocate LO Allocate L1 Allocate L2 Allocate L3 Allocate L4 Allocate L5 Allocate L6 Allocate L7 B2 1 Figure 3 5 PLRU Replacement Algorithm Chapter 3 L1 Instruction and Data Cache Operation 3 19 ...

Page 167: ... 3 2 PLRU Bit Update Rules If the Then the PLRU bits are Changed to Current Access is BO B1 B2 B3 B4 B5 B6 To La 1 1 x 1 x x x L1 1 1 x a x x x L2 1 a x x 1 x x L3 1 a x x a x x L4 a x 1 x x 1 x L5 a x 1 x x a x L6 a x a x x x 1 L7 a x a x x x a x Does not change If all eight blocks are valid then a block is selected for replacement according to the PLRU bit encodings shown in Table 3 3 3 20 Table...

Page 168: ...plete 3 5 3 Data Cache Block Fill Operations The MPC750 s data cache blocks are filled in four beats of 64 bits each with the critical double word loaded first The data cache is not blocked to internal accesses while the load caused by a cache miss completes This functionality is sometimes referred to as hits under misses because the cache can service a hit while a cache miss fill is waiting to co...

Page 169: ...enure is used for the load operation The enveloped high priority cache block push feature defines a bus signal data bus write only DBWO which when asserted with a qualified data bus grant indicates that the resulting data tenure should be used for the store operation instead This signal is described in Section 8 10 Using Data Bus Write Only Note that the enveloped copy back operation is an interna...

Page 170: ...rdered in the following manner Beat o 2 3 C D A B Figure 3 6 Double Word Address Ordering Critical Double Word First 3 6 1 Read Operations and the MEl Protocol The MEl coherency protocol affects how the MPC750 data cache performs read operations on the 60x bus All reads except for caching inhibited reads are encoded on the bus as read with intent to modify RWITM to force flushing of the addressed ...

Page 171: ...nstructions refer to Chapter 2 MPC750 Processor Programming Model in this book and Chapter 8 Instruction Set in The Programming Environments Manual Table 3 4 provides an overview of the bus operations initiated by cache control instructions Note that Table 3 4 assumes that the WIM bits are set to 001 that is the cache is operating in write back mode caching is permitted and coherency is enforced T...

Page 172: ... transactions that cross an aligned 32 byte boundary must present a new address onto the bus at that boundary for proper snoop operation by the MPC750 or they must operate noncoherently with respect to the MPC750 As bus operations are performed on the bus by other bus masters the MPC750 bus snooping logic monitors the addresses and transfer attributes that are referenced The MPC750 snoops the bus ...

Page 173: ...ache or memory queues The MPC750 may also retry a bus transaction if it is unable to snoop the transaction on that cycle due to internal resource conflicts Additional snoop action may be forwarded to the cache as a result of a snoop hit in some cases a cache push of modified data or a cache block invalidation 3 6 4 Snoop Response to 60x Bus Transactions There are several bus transaction types defi...

Page 174: ...ing allowed push or snoop copy back If the address hits in the cache the cache block is placed in the invalid I state killing modified data that may have been in the block If the address misses in the cache no action is taken Any reservation associated with the address is canceled Read 01010 A read operation is used by most single beat and burst load transactions on the bus For single beat caching...

Page 175: ... in response to Iwarx instructions and generate the same snooping responses as read operations Read with intent to mo 11110 The RWITM atomic operations appear on the bus in response to dify atomic stwcx instructions and generate the same snooping responses as RWITM operations Reserved 00011 Reserved 00111 Read with no intent to 01011 A RWNITC operation is issued to acquire exclusive use of a memor...

Page 176: ... DMA write operations with this encoding but marked global GBL asserted and thus must be snooped Table 3 6 summarizes the address and transfer attribute information presented on the bus by the MPC750 for various master or snoop related transactions Table 3 6 Address Transfer Attribute Summary Bus Transaction A O 31 TT O 4 TBST TSIZ o 2 GBl WT cr Instruction fetch operations Burst caching allowed P...

Page 177: ... or 1 WIM state implied by transaction type in table For instruction fetches reflection of the M bit must be enabled through HIDO IFEM A Atomic high if Iwarx low otherwise S Transfer size Special instructions listed may not generate bus transactions depending on cache state 3 7 Bus Interface The bus interface buffers bus requests from the instruction and data caches and executes the requests per t...

Page 178: ...bility A conceptual block diagram of the bus interface is shown in Figure 3 7 The address register queues in the figure hold transaction requests that the bus interface may issue on the bus independently of the other requests The bus interface may have up to two transactions operating on the bus at any given time through the use of address pipelining I Cache I I I I D Cache I I i BIU H I Cache II ...

Page 179: ...ad push Write with kill sector to write queue Iwarx Read Acts like other reads but bus operation uses special encoding Store Write No OOx I Same Cast out of modified Write with kill T O block if necessary Pass RWITM to RWITM memory queue Store Write No OOx E M M Write data to cache T O Store stwcx Write No 10x I Same Pass single beat write Write with flus T O to memory queue h Store stwcx Write No...

Page 180: ...bst Datacache No xxx I E Same CRTRY debst block store Pass clean Clean Same Same No action debst Datacache No xxx M E Push block to write Write with kill block store queue debz Datacache No xix x x Alignment trap block set to zero debz Datacache No 10x x x Alignment trap blocksetto zero debz Datacache Yes OOx I Same CRTRYdebz blocksetto zero Cast out of modified Write with kill block Pass kill Kil...

Page 181: ...xx I E Write data_in to cache double word al dump igned Four beat write Reload No xxx I M Write data_in to cache double word al dump igned E I Snoop No xxx E I State change only write or kill committed M I Snoop No xxx M I State change only kill committed Push Snoop No xxx M I Conditionally push Write with kill M I flush Push Snoop No xxx M E Conditionally push Write with kill M E clean tlbie TLB ...

Page 182: ...sable some exception conditions The PowerPC architecture requires that exceptions be taken in program order therefore although a particular implementation may recognize exception conditions out of order they are handled strictly in order with respect to the instruction stream When an instruction caused exception is recognized any unexecuted instructions that appear earlier in the instruction strea...

Page 183: ...asynchronous exceptions and sometimes to the event that causes the exception Also the PowerPC architecture uses the word exception to refer to IEEE defined floating point exception conditions that may cause a program exception to be taken see Section 4 5 7 Program Exception Ox00700 The occurrence of these IEEE exceptions may not cause an exception to be taken IEEE defined exceptions are referred t...

Page 184: ...is attempted in little endian mode An operand of a dcbz instruction is on a page that is write through or cache inhibited for a virtual mode access An attempt to execute a dcbz instruction occurs when the cache is disabled Program 00700 As defined by the PowerPC architecture Floating point 00800 As defined by the PowerPC architecture unavailable Oecrementer 00900 As defined by the PowerPC architec...

Page 185: ... taken Note that the MPC750 does not implement an exception of this type 4 Maskable asynchronous exceptions external decrementer thermal management system management performance monitor and interrupt exceptions are delayed until higher priority exceptions are taken The following list of exception categories describes how the MPC750 handles exceptions up to the point of signaling the appropriate in...

Page 186: ... and the current instruction stream is allowed to drain out of the machine If completing any of the instructions in this stream causes an exception that exception is taken and the instruction fetch exception is discarded but may be encountered again when instruction processing resumes Otherwise once all pending instructions have executed and a recoverable state is reached the lSI exception is take...

Page 187: ...on condition breakpoint 1 Program Occurrence of an illegal instruction privileged instruction or trap exception condition Note that floating point enabled program exceptions have lower priority 2 System call System Call sc instruction 3 Floating point Any floating point unavailable exception condition unavailable 4 Program A floating point enabled exception condition lowest priority program except...

Page 188: ...s Depending on the exception this may be the address in SRRO or at the next address in the program flow All instructions in the program flow preceding this one will have completed execution and no subsequent instruction will have begun execution This may be the address of the instruction that caused the exception or the next one as in the case of a system call trace or trap exception The SRRO regi...

Page 189: ...errupts and decrementer exception conditions 1 The processor is enabled to take an external interrupt or the decrementer exception 17 PR Privilege level 0 The processor can execute both user and supervisor level instructions 1 The processor can only execute user level instructions 18 FP Floating point available 0 The processor prevents dispatch of floating paint instructions including floating poi...

Page 190: ... not a marked process 1 Process is a marked process MPC750 specific defined as reserved by the PowerPC architecture For more information about the performance monitor see Section 4 5 13 Performance Monitor Interrupt OxOOFOO 30 RI Indicates whether system reset or machine check exception is recoverable 0 Exception is not recoverable 1 Exception is recoverable The RI bit indicates whether from the p...

Page 191: ...nition of conditions causing those exceptions A machine check exception can occur only if the machine check enable bit MSR ME is set IfMSR ME is cleared the processor goes directly into checkstop state when a machine check exception condition occurs Individual machine check exceptions can be enabled and disabled through bits in the HIDO register which is described in Table 4 8 System reset excepti...

Page 192: ...t to the processor In each exception handler When enough state information has been saved that a machine check or system reset exception can reconstruct the previous state set MSR RI In each exception handler Clear MSR RI set SRRO and SRRI appropriately and then execute rfi Note that the RI bit being set indicates that with respect to the processor enough processor state data remains valid for the...

Page 193: ...e stwcx instruction clears any outstanding reservations ensuring that an lwarx instruction in an old process is not paired with an stwcx instruction in a new one The operating system should set MSR RI as described in Section 4 3 3 Setting MSR RI 4 5 Exception Definitions Table 4 6 shows all the types of exceptions that can occur with the MPC750 and MSR settings when the processor goes into supervi...

Page 194: ... implements the system reset exception as defined in the PowerPC architecture OEA The system reset exception is a nonmaskable asynchronous exception signaled to the processor through the assertion of system defined signals In the MPC750 the exception is signaled by the assertion of either the SRESET or HRESET inputs described more fully in Chapter 7 Signal Descriptions Table 4 7 lists register set...

Page 195: ...t POR in which case TRST must also be asserted but can also be used to restart a running processor The HRESET signal must be asserted during power up and must remain asserted for a period that allows the PLL to achieve lock and the internal logic to be reset This period is specified in the hardware specifications The MPC750 internal state after the hard reset interval is defined in Table 2 19 If H...

Page 196: ...op if MSR ME 0 or a machine check exception if MSR ME 1 EBA and EBO allow the processor to operate with memory subsystems that do not generate parity 15 NHR Not hard reset software use only 0 A hard reset occurred if software had previously set this bit 1 A hard reset has not occurred A TEA indication on the bus can result from any load or store operation initiated by the processor In general TEA ...

Page 197: ...R 0 SE 0 IR 0 LE Set to value of ILE Note that to handle another machine check exception the exception handler should set MSR ME as soon as it is practical after a machine check exception is taken Otherwise subsequent machine check excep tions cause the processor to enter the checkstop state The machine check exception is usually unrecoverable in the sense that execution cannot resume in the conte...

Page 198: ...tion exists and an attempt to fetch the next instruction fails This exception is implemented as it is defined by the PowerPC architecture OEA and is taken for the following conditions The effective address cannot be translated The fetch access is to a no execute segment SR N 1 The fetch access is to guarded storage and MSR IR 1 The fetch access is to a segment for which SR T is set The fetch acces...

Page 199: ...3 DSI Exception Ox00300 4 5 7 Program Exception Ox00700 The MPC750 implements the program exception as it is defined by the PowerPC architecture OEA A program exception occurs when no higher priority exception exists and one or more of the exception conditions defined in the OEA occur The MPC750 invokes the system illegal instruction program exception when it detects any instruction from the illeg...

Page 200: ...on exists a decrementer exception condition occurs for example the decrementer register has completed decrementing and MSR EE 1 In the MPC750 the decrementer register is decremented at one fourth the bus clock rate Register settings for this exception are described in Chapter 6 Exceptions in The Programming Environments Manual When a decrementer exception is taken instruction fetching resumes at o...

Page 201: ...s misses in either the instruction cache or the data cache instructions dispatched to a particular execution unit mispredicted branches and other occurrences The count of such events can be used to trigger the performance monitor exception The performance monitor facility is not defined by the PowerPC architecture The performance monitor can be used for the following To increase system performance...

Page 202: ...errupt follows the normal PowerPC exception model with a defined exception vector offset OxOOFOO The priority of the performance monitor interrupt lies between the external interrupt and the decrementer interrupt see Table 4 3 The contents of the SIA are described in Section 2 1 2 4 Performance Monitor Registers The performance monitor is described in Chapter 11 Performance Monitor 4 5 14 Instruct...

Page 203: ...n if the breakpoint is enabled by the mtspr IABR immediately preceding it The MPC750 also cannot block a breakpoint response on the context synchronizing instruction if the breakpoint was disabled by the mtspr IABR instruction immediately preceding it The format of the IABR register is shown in Section 2 1 2 1 Instruction Address Breakpoint Register IABR When an instruction address breakpoint exce...

Page 204: ...em management interrupt is signaled to the MPC750 by the assertion of an input signal The system management interrupt signal SMI is expected to remain asserted until the interrupt is taken If SMI is negated early recognition of the interrupt request is not guaranteed After the MPC750 begins execution of the system management interrupt handler the system can safely negate SMI After the assertion of...

Page 205: ...eared 16 31 Loaded with equivalent MSR bits MSR POW 0 FP 0 BE 0 DR 0 ILE ME FE1 0 PM 0 EE 0 FEO 0 IP RI 0 PR 0 SE 0 IR 0 LE Set to value of ILE The thermal management interrupt is similar to the system management and external interrupts The MPC750 requires the next instruction in program order to complete or take an exception blocks completion of any following instructions and allows the completed...

Page 206: ...rms of the segment descriptors and page tables PowerPC processors use to locate the effective to physical address mapping for memory accesses The segment information translates the effective address to an interim virtual address and the page table information translates the interim virtual address to a physical address The segment descriptors used to generate the interim virtual addresses are stor...

Page 207: ... mechanism for translating blocks as large as 256 Mbytes from the 32 bit effective address space into the physical memory space This can be used for translating large address ranges whose mappings do not change frequently Segmented address translation The 32 bit effective address is extended to a 52 bit virtual address by substituting 24 bits of upper address bits from the segment register for the...

Page 208: ...electable as no execute Pages selectable as user supervisor and read only or guarded Blocks selectable as user supervisor and read only or guarded Page history Architecturally defined Referenced and changed bits defined and maintained Page address Architecturally defined Translations stored as PTEs in hashed page tables in memory translation Page table size determined by mask in SDR1 register TLBs...

Page 209: ...on chip TLBs with the following characteristics 128 entries two way set associative 64 x 2 LRU replacement Data TLB supports the DMMU instruction TLB supports the IMMU Hardware TLB update Hardware update of referenced R and changed C bits in the translation table In the event of a TLB miss the hardware attempts to load the TLB based on the results of a translation table search operation Figure 5 2...

Page 210: ...nality of the MMUs The figures show how address bits A 20 26 index into the on chip instruction and data caches to select a cache set The remaining physical address bits are then compared with the tag fields comprised of bits PA 0 19 of the two selected cache blocks to determine if a cache hit has occurred In the case ofa cache miss on the MPC750 the instruction or data access is then forwarded to...

Page 211: ... Optional PA Q 31 Figure 5 1 MMU Conceptual Block Diagram 32 Bit Implementations 5 6 MPC750 RISC Microprocessor User s Manual ...

Page 212: ...Instruction Unit A 20 31 PA Q 31 0 Select A 2G 26 127 7 ICache Ta PA O 19 O I Cache Hit Miss Figure 5 2 MPC750 Microprocessor IMMU Block Diagram Chapter 5 Memory Management 5 7 ...

Page 213: ...5 8 A 2Q 31 0 Select A 20 26 127 PA O 31 DCache 7 Tag PA Q 19 O DCache HiVMiss Figure 5 3 MPC750 Microprocessor DMMU Block Diagram MPC750 RISC Microprocessor User s Manual ...

Page 214: ... be to the direct store interface space the MPC750 takes a DSI exception if it is a data access see Section 4 5 3 DSI Exception Ox00300 and takes an lSI exception ifit is an instruction access see Section 4 5 4 lSI Exception Ox00400 For memory accesses translated by a segment descriptor the interim virtual address is generated using the information in the segment descriptor Page address translatio...

Page 215: ...ical Address See Section 5 2 rO______ ____ 3 1 rO______ L______3 1 rO______ ______3 1 Physical Address Physical Address Physical Address Figure 5 4 Address Translation Types When the processor generates an access and the corresponding address translation enable bit in MSR is cleared the resulting physical address is identical to the effective address and all other translation mechanisms are ignore...

Page 216: ... option provided in the segment register lets the operating system program determine whether instructions can be fetched from an area of memory The remaining options are enforced based on a combination of information in the segment descriptor and the page table entry Thus the supervisor only option allows only read and write operations generated while the processor is operating in supervisor mode ...

Page 217: ...or the changed bit is not set the hardware automatically sets both bits in the translation table In addition when the address translation of a store operation hits in the DTLB the MPC750 checks the state of the changed bit If the bit is not already set the hardware automatically updates the DTLB and the translation table in memory to set the changed bit For more information see Section 5 4 1 Page ...

Page 218: ...ation BAT Array Miss BAT Array See The Programming Hit mentsManUal Perform Address Translation with Segment Descriptor See Figure 5 6 Access Faulted ____ Access Access Permitted Protected Continue Access to Memory Subsystem Figure 5 5 General Flow of Address Translation Real Addressing Mode and Block Note that if the BAT array search results in a hit the access is qualified with the appropriate pr...

Page 219: ... 16 segment registers Note that the MPC750 does not implement the direct store interface and accesses to these segments cause a DSI or lSI exception In addition Figure 5 6 also shows the way in which the no execute protection is enforced if the N bit in the segment descriptor is set and the access is an instruction fetch the access is faulted as described in Chapter 7 Memory Management in The Prog...

Page 220: ...th N Bit Set in Segment Descriptor No Execute DSIlISI Exception THLB See Figure 5 8 It __ See Figure 5 9 PTE Found ___1___ I Load TLB Entry Access Permitted Continue Access to Memory Subsystem Access Protected Access Faulted Optional to the PowerPC architecture Implemented in the MPC750 In the case 01 instruction accesses causes lSI exception Figure 5 6 General Flow of Page and Direct Store Interf...

Page 221: ...ption is generated If the PTE is not found by the table search operation a page fault condition exists and an lSI or DSI exception occurs so software can handle the page fault 5 1 7 MMU Exceptions Summary To complete any memory access the effective address must be translated to a physical address As specified by the architecture an MMU exception condition occurs if this translation fails for one o...

Page 222: ...truction fetch from guarded Attempt to fetch instruction when MSR IR 1 lSI exception memory and either matching xBAT G 1 or no SRR1 3 1 matching BAT entry and PTE G 1 In addition to the translation exceptions there are other MMU related conditions some of them defined as implementation specific and therefore not required by the architecture that can cause an exception to occur These exception cond...

Page 223: ...exception some load store stmw stwcx Imw Iwarx eciwx of these cases are or ecowx instruction operand is not implementation specific word aligned 5 1 8 MMU Instructions and Register Summary The MMU instructions and registers allow the operating system to set up the block address translation areas and the page tables in memory Note that because the implementation of TLBs is optional the instructions...

Page 224: ...n depending on the setting of HIDxx execution of this instruction causes all entries in the congruence class corresponding to the EA to be invalidated in the other processors attached to the same bus Software must ensure that instruction fetches or memory references to the virtual pages specified by the tlbie instruction have been completed prior to executing the tlbie instruction tlbsync TLB Sync...

Page 225: ...ddress is treated as the physical address and is passed directly to the memory subsystem as described in Chapter 7 Memory Management in The Programming Environments Manual Note that the default WIMG bits ObOOll cause data accesses to be considered cacheable I 0 and thus load and store accesses are weakly ordered This is the case even if the data cache is disabled in the HIDO register as it is out ...

Page 226: ...emory in the PowerPC OEA is divided into 256 Mbyte segments This segmented memory model provides a way to map 4 Kbyte pages of effective addresses to 4 Kbyte pages in physical memory page address translation while providing the programming flexibility afforded by a large virtual address space 52 bits The segment page address translation mechanism may be superseded by the block address translation ...

Page 227: ...execute if there is a TLBIBAT hit or if the processor is in real addressing mode In case of a TLB or BAT miss these instructions are treated as no ops they do not initiate a table search operation and they do not set either the R or C bits As defined by the PowerPC architecture the referenced and changed bits are updated as if address translation were disabled real addressing mode Ifthese update a...

Page 228: ... is set only when a store operation is allowed by the page memory protection mechanism and the store is guaranteed to be in the execution path unless an exception other than those caused by the se rfi or trap instructions occurs Furthermore the following conditions may cause the C bit to be set The execution of an stwex instruction is allowed by the memory protection mechanism but a store operatio...

Page 229: ...and C Bit Settings Causes Setting of R BH Causes Setting ot C Bit Priority Scenario OEA MPC750 OEA MPC750 1 No execute protection violation No No No No 2 Page protection violation Maybe Yes No No 3 Out ol order instruction fetch or load operation Maybe No No No 4 Out ol order store operation Would be required Maybe1 No No No by the sequential execution model in the absence of system caused or impr...

Page 230: ...o MMUs IMMU and DMMU that operate in parallel some of the MMU resources are shared and some are actually duplicated shadowed in each MMU to maximize performance For example although the architecture defines a single set of segment registers for the MMU the MPC750 maintains two identical sets of segment registers one for the IMMU and one for the DMMU when an instruction that updates the segment reg...

Page 231: ...at which point the access is no longer out of order When the matching PTE is found in memory it is loaded into the TLB entry selected by the least recently used LRU replacement algorithm and the translation process begins again this time with a TLB hit To uniquely identify a TLB entry as the required PTE the PTE also contains four more bits of the page index EA 0 13 in addition to the API bits in ...

Page 232: ...the WIMG bits are then used as attributes for the access Although address translation is disabled on a reset condition the valid bits of TLB entries are not automatically cleared Thus TLB entries must be explicitly cleared by the system software with the tlbie instruction before the valid entries are loaded and address translation is enabled Also note that the segment registers do not have a valid...

Page 233: ...5 4 4 Page Address Translation Summary Figure 5 8 provides the detailed flow for the page address translation mechanism The figure includes the checking of the N bit in the segment descriptor and then expands on the TLB Hit branch of Figure 5 6 The detailed flow for the TLB Miss branch of Figure 5 6 is described in Section 5 4 5 Page Table Search Operation Note that as in the case of block address...

Page 234: ...ent Descriptor No Execute debz wtthWorl 1 Otherwise Alignment Exception Check Page Memory Protection Violation Conditions Access Permitted See The Programming Environments Manual Access Prohibited See The Programming Environments Manual PTE C 0 Otherwise Page Memory Protection Violation See Figure 5 9 Continue Access to Memory Sub system with WIMG Bits from PTE Figure 5 8 Page Address Translation ...

Page 235: ...page number VPN of the access The VPN is the VSID concatenated with the page index field of the virtual address For a match to occur the following must be true PTE H 0 PTE V 1 PTE VSID VA 0 23 PTE API VA 24 29 4 If a match is not found step 3 is repeated for each of the other seven PTEs in the primary PTEG If a match is found the table search process continues as described in step 8 If a match is ...

Page 236: ...ult exception condition occurs either an lSI exception or a DSI exception Figure 5 9 and Figure 5 10 show how the conceptual model for the primary and secondary page table search operations described in The Programming Environments Manual are realized in the MPC750 Figure 5 9 shows the case of a dcbz instruction that is executed with W 1 or I l and that the R bit may be updated in memory if requir...

Page 237: ... Page Table Search Hit Otherwise RJlag 1 Access Permitted Otherwis0tore Operation with PTE C 0 Access Prohibited Otherwise I therwise R_Flag 1 Alignment Exception 5 32 RJlag 1 PTE R 1 Update PTE R in Memory Page Table Search Complete PTE 1 Update PTE C in Memory Also Update PTE R in Memory if R_Flag 1 Page Table Search Complete PTE R 1 Update PTE R in Memory Memory Protection Violation Figure 5 9 ...

Page 238: ...te through or cache inhibited The MMU also detects alignment exceptions caused by the dcbz instruction and prevents the changed bit in the PTE from being updated erroneously in these cases If an MMU register is being accessed by an instruction in the instruction stream the IMMU stalls for one translation cycle to perform that operation The sequencer serializes instructions to ensure the data corre...

Page 239: ...plicitly altering certain MSR bits using the mtmsr instruction or explicitly altering PTEs or certain system registers may have the side effect of changing the effective or physical addresses from which the current instruction stream is being fetched This kind of side effect is defined as an implicit branch Implicit branches are not supported and an attempt to perform one causes boundedly undefine...

Page 240: ...chapter Branch prediction The process of guessing whether a branch will be taken Such predictions can be correct or incorrect the term predicted as it is used here does not imply that the prediction is correct successful The PowerPC architecture defines a means for static branch prediction as part of the instruction encoding Branch resolution The determination of whether a branch is taken or not t...

Page 241: ... becomes available for the next instruction Although an individual instruction may take many cycles to complete the number of cycles is called instruction latency pipelining makes it possible to overlap the processing so that the throughput number of instructions completed per cycle is greater than if pipelining were not implemented Program order The order of instructions in an executing program M...

Page 242: ...er cannot be flushed If an exception occurs these buffers must write back before the exception is taken 6 2 Instruction Timing Overview The MPC750 design minimizes average instruction execution latency the number of clock cycles it takes to fetch decode dispatch and execute instructions and make the results available for a subsequent instruction Some instructions such as loads and stores access me...

Page 243: ... pipelines The MPC750 contains the following execution units that operate independently and in parallel Branch processing unit BPU Integer unit 1 IUl executes all integer instructions Integer unit 2 IU2 executes all integer instructions except multiplies and divides 64 bit floating point unit FPU Load store unit LSU System register unit SRU The MPC750 can retire two instructions on every clock cyc...

Page 244: ...h instructions from system memory and include the processor to bus clock ratio the amount of bus traffic and whether any cache coherency operations are required Because there are so many variables unless otherwise specified the instruction timing examples below assume optimal performance that the instructions are available in the instruction queue in the same clockcycle that they are requested The...

Page 245: ...on stream is fetched The complete stage ends when the instruction is retired Two instructions can be retired per cycle Instructions are retired only from the two lowest completion queue entries CQO and CQ1 The notation conventions used in the instruction timing examples are as follows Fetch The fetch stage includes the time between when an instruction is requested and when it is brought into the i...

Page 246: ...spatch In Completion Complete Retire2 Entry Queue2 1Several integer instructions such as multiply and divide instructions require multiple cycles in the execute stage 2Only those branch instructions that update the LR or CTR take an entry in the completion queue Figure 6 3 MPC750 Microprocessor Pipeline Stages 6 3 Timing Considerations The MPC750 is a superscalar processor as many as three instruc...

Page 247: ...scribes this process in greater detail 6 3 1 General Instruction Flow As many as four instructions can be fetched into the instruction queue IQ in a single clock cycle Instructions enter the IQ and are issued to the various execution units from the dispatch queue The MPC750 tries to keep the IQ full at all times unless instruction cache throttling is operating The number of instructions requested ...

Page 248: ...e the strength of the next prediction This dynamic branch prediction is not defined by the PowerPC architecture To reduce aliasing only predicted branches update the BHT entries Dynamic branch prediction is enabled by setting HIDO BHT otherwise static branch prediction is used Static branch prediction Static branch prediction is defined by the PowerPC architecture and involves encoding the branch ...

Page 249: ...cle Instruction Queue l l l l l In program order r I I Completion Queue Assignment Reservation Stations 1 1 I I LSU Dispatch Maximum 2instructions per clock cycle 1instruction per unit IU1 IU2 SRU Complete Retire Figure 6 4 Instruction Flow Diagram 6 10 MPC750 RISC Microprocessor User s Manual ...

Page 250: ...hits the instruction cache it takes only one clock cycle after the request for as many as four instructions to enter the instruction queue Note that the cache is not blocked to internal accesses during a cache reload completes hits under misses The critical double word is written simultaneously to the cache and forwarded to the requesting unit minimizing stalls due to load delays Figure 6 5 shows ...

Page 251: ..._ 18 17 14 16 16 18 13 15 15 17 12 14 14 16 11 13 13 15 Completion Oueue 12 12 14 o 3 2 1 o 6 3 2 6 3 2 10 8 9 7 8 6 7 3 6 11 11 10 10 9 9 8 8 7 7 Figure 6 5 Instruction Timing Cache Hit 13 12 11 10 9 The instruction timing for this example is described cycle by cycle as follows 14 13 12 14 11 13 O In cycle 0 instructions 0 3 are fetched from the instruction cache Instructions 0 and 1 are placed i...

Page 252: ... last of the three FPU execute stages Instruction 2 has executed but must remain in the completion queue until instruction 1 completes Instruction 3 replaces instruction 1 in the second stage of the FPU and instruction 6 replaces instruction 3 in the first stage Also as will be shown in cycle 4 there is a single cycle stall that occurs when the FPU pipeline is full Because there were three vacanci...

Page 253: ...n this cycle because the instruction queue was full on the previous clock cycle 6 3 2 3 Cache Miss Figure 6 6 shows an instruction fetch that misses both the on chip cache and L2 cache A processor bus clock ratio is 1 2 is used The same instruction sequence is used as in Section 6 3 2 2 Cache Hit however in this example the branch target instruction is not in either the L1 or L2 cache Because the ...

Page 254: ...2 3 3 2 2 0 0 3 7 6 10 add I 11 add I 12fadd 13fadd i 7 6 9 8 9 8 7 7 6 6 Instructions 5and 6are not in the 10 in clock cycle 5 Here the fetch stage shows cache latency Figure 6 6 Instruction Timing Cache Miss 6 3 2 4 L2 Cache Access Timing Considerations MPC750 Only Ifan instruction fetch misses both the BTIC and the on chip instruction cache the MPC750 next looks in the L2 cache If the requested...

Page 255: ...queue so instructions can be dispatched to other execution units Execution begins during the same clock cycle that the rename buffer is updated with the data the instruction is dependent on If both instructions in IQO and IQl require the same execution unit the instruction in IQl cannot be dispatched until the first instruction proceeds through the pipeline and provides the subsequent instruction ...

Page 256: ...eding it in the completion queue have been resolved correctly If a branch prediction was incorrect the instructions following the branch are flushed from the completion queue and any results of those instructions are flushed from the rename registers 6 3 3 2 Instruction Serialization Although the MPC750 can dispatch and complete two instructions per cycle so called serializing instructions limit d...

Page 257: ...ed by many factors including the following Whether the branch is taken Whether instructions in the target stream typically the first two instructions in the target stream are in the branch target instruction cache BTIC Whether the target instruction stream is in the on chip cache Whether the branch is predicted Whether the prediction is correct 6 4 1 1 Branch Folding and Removal of Fall Through Br...

Page 258: ...ry access is required the latency of which is dependent on several factors such as processorlhus clock ratios In most cases new instructions arrive in the IQ before the execution units become idle Branch Folding Taken BranchIBTlC Hit Clock 0 Clock 1 Clock 2 105 104 a 103 a 102 101 a 100 a F iE i Branch Folding Taken BranchlBTlC Miss Clock 0 Clock 1 Clock 2 105 104 a 103 a 102 101 a 100 a Figure 6 ...

Page 259: ...e completion queue either by branch folding in the case of taken branches or by removing fall through branch instructions at dispatch in the case of non taken branches However branch instructions that update the architected LR and CTR must do so in program order and therefore must perform write back in the completion stage like the instructions that update the FPRs and GPRs Branch instructions tha...

Page 260: ... The number of instructions that can be executed after the issue of a predicted branch instruction is limited by the fact that no instruction executed after a predicted branch may actually update the register files or memory until the branch is completed That is instructions may be issued and executed but cannot reach the write back stage in the completion unit When an instruction following a pred...

Page 261: ... instruction processing until the condition is known the MPC750 uses the instruction encoding to predict whether the branch is likely to be taken and begins fetching and executing along that path When the branch condition is known the prediction is evaluated Ifthe prediction was correct program flow continues along that path otherwise the processor flushes any instructions and their results from t...

Page 262: ... I I I T5 T5 8 T4 T4 7 T3 T3 6 T2 T2 5 Tl 8 8 TO Tl 7 7 3 TO 6 6 6 2 3 5 5 5 8 7 6 5 Instructions 5and 6are not in the 10 in clock cycle 5 Here the fetch stage shows cache latency Figure 6 10 Branch Instruction Timing o During clock cycle 0 instructions 0 and 1 are dispatched to their respective execution units Instruction 2 is a branch instruction that updates the CTR It is predicted as not taken...

Page 263: ... stream instruction 5 the same instruction that was fetched in clock cycle 1 is brought back into the IQ from the instruction cache along with three others not all of which are shown 6 4 2 Integer Unit Execution Timing The MPC750 has two integer units The lUI can execute all integer instructions and the IU2 can execute all integer instructions except multiply and divide instructions As shown in Fi...

Page 264: ... the cache line refill Table 6 8 gives load and store instruction execution latencies 6 4 6 Effect of Operand Placement on Performance The PowerPC YEA states that the placement location and alignment of operands in memory may affect the relative performance of memory accesses and in some cases affect it significantly The effects memory operand placement has on performance are shown in Table 6 1 Th...

Page 265: ...multiple bus transfers 4 Poor means that an alignment exception occurs 6 4 7 Integer Store Gathering The MPC750 perfonns store gathering for write through operations to nonguarded space It perfonns cache inhibited stores to nonguarded space for 4 byte word aligned stores These stores are combined in the LSD to fonn a double word and are sent out on the 60x bus as a single beat operation However st...

Page 266: ...ry Coherency To minimize the effect of bus contention the PowerPC architecture defines WIM bits that are used to configure memory regions as caching enforced or caching inhibited Accesses to such memory locations never update the on chip cache If a cache inhibited access hits the on chip cache the cache block is invalidated If the cache block is marked modified it is copied back to memory before b...

Page 267: ...t is undesirable to allocate a cache block on a cache miss Chapter 3 LI Instruction and Data Cache Operation describes the caches memory configuration and snooping in detail 6 5 2 Effect of TLB Miss If a page address translation is not in a TLB the MPC750 hardware searches the page tables and updates the TLB when a translation is found Table 6 2 shows the estimated latency for the hardware TLB loa...

Page 268: ...ts being busy Avoid scheduling high latency instructions close together Interspersing single cycle latency instructions between longer latency instructions minimizes the effect that instructions such as integer divide and multiply can have on throughput Avoid using serializing instructions Schedule instructions to avoid dispatch stalls Six instructions can be tracked in the completion queue theref...

Page 269: ...xecution unit available Needed GPR rename registers available Needed FPR rename registers available Completion queue is not full A completion serialized instruction is not being executed Requirements for dispatching from IQ l are as follows Instruction in IQ O must dispatch Instruction dispatched by IQ O is not completion or refetch serialized Needed execution unit is available after dispatch from...

Page 270: ...3 describes branch instruction latencies Table 6 3 Branch Instructions Mnemonic Primary Extended Latency b l a 18 Unless these instructions update either the CTR or the LR branch bc l a 16 operations are folded if they are either taken or predicted as taken They fall through if they are not taken or predicted as not taken bcctr l 19 528 bclr l 19 16 Table 6 4 lists system register instruction late...

Page 271: ...be asserted In most systems T LB I S Y N C is always asserted so the instruction is a no op Table 6 5 lists condition register logical instruction latencies Table 6 5 Condition Register Logical Instructions Mnemonic Primary Extended Unit Cycles Serialization crand 19 257 SRU 1 Execution crandc 19 129 SRU 1 Execution creqv 19 289 SRU 1 Execution crnand 19 225 SRU 1 Execution crnor 19 33 SRU 1 Execu...

Page 272: ...60 IU1 1U2 1 andi 28 IU1 1U2 1 andis 29 IU1 1U2 1 and 31 28 IUlIIU2 1 cmp 31 0 IU1 1U2 1 cmpi 11 IU1 1U2 1 cmpl 31 32 IU1 1U2 1 cmpli 10 IU1 1U2 1 cntlzw 31 26 IU1 1U2 1 divwu o 31 459 IU1 19 divw o 31 491 IU1 19 eqv 31 284 IU1 1U2 1 extsb 31 954 IUlIIU2 1 extsh 31 922 IUlIIU2 1 mUlhwu 31 11 IUlIIU2 2 3 4 5 6 mulhw 31 75 IU1 1U2 2 3 4 5 multi 7 IU1 2 3 mull o 31 235 IU1 2 3 4 5 nand 31 476 IU1 1U2...

Page 273: ...27 IU1 1U2 1 xor 31 316 IU1 1U2 1 Table 6 7 shows latencies for floating point instructions Pipelined floating point instructions are shown with number of clocks in each pipeline stage separated by dashes Floating point instructions with a single entry in the cycles column are not pipelined when the FPU executes these nonpipelined instructions it remains busy for the full duration of the instructi...

Page 274: ...2 1 1 fmuls 59 25 FPU 1 1 1 fmul 63 25 FPU 2 1 1 fnabs 63 136 FPU 1 1 1 fneg _ 63 40 FPU 1 1 1 fnmadds 59 31 FPU 1 1 1 fnmadd _ 63 31 FPU 2 1 1 fnmsubs 59 30 FPU H 1 fnmsub 63 30 FPU 2 1 1 fres 59 24 FPU 10 frsp 63 12 FPU 1 1 1 frsqrte _ 63 26 FPU 1 1 1 fsel 63 23 FPU 1 1 1 fsubs 59 20 FPU 1 1 1 fsub 63 20 FPU 1 1 1 mcrfs 63 64 FPU 1 1 1 Execution mffs 63 583 FPU 1 1 1 Execution mtfsbO _ 63 70 FPU...

Page 275: ... LSU 2 1 debtst 31 246 LSU 2 1 debz 31 1014 LSU 3 61 2 Execution eeiwx 31 310 LSU 2 1 eeowx 31 438 LSU 2 1 icbi 31 982 LSU 3 41 Execution Ibz 34 LSU 2 1 Ibzu 35 LSU 2 1 Ibzux 31 119 LSU 2 1 Ibzx 31 87 LSU 2 1 Ifd 50 LSU 2 1 Ifdu 51 LSU 2 1 Ifdux 31 631 LSU 2 1 Ifdx 31 599 LSU 2 1 Ifs 48 LSU 2 1 Ifsu 49 LSU 2 1 Ifsux 31 567 LSU 2 1 Ifsx 31 535 LSU 2 1 Iha 42 LSU 2 1 Ihau 43 LSU 2 1 Ihaux 31 375 LSU...

Page 276: ... Iwzx 31 23 LSU 2 1 stb 38 LSU 2 1 stbu 39 LSU 2 1 stbux 31 247 LSU 2 1 stbx 31 215 LSU 2 1 stfd 54 LSU 2 1 stfdu 55 LSU 2 1 stfdux 31 759 LSU 2 1 stfdx 31 727 LSU 2 1 stfiwx 31 983 LSU 2 1 stfs 52 LSU 2 1 stfsu 53 LSU 2 1 stfsux 31 695 LSU 2 1 stfsx 31 663 LSU 2 1 sth 44 LSU 2 1 sthbrx 31 918 LSU 2 1 sthu 45 LSU 2 1 sthux 31 439 LSU 2 1 sthx 31 407 LSU 2 1 stmw 47 LSU 2 n 3 Execution stswi 31 725...

Page 277: ... cache ops Throughput may be larger than the initial latency as more cycles may be needed to complete the instruction to the cache which stays busy keeping subsequent cache ops from executing 2 The throughput number of 6 cycles for dcbz assumes it is to nonglobal M 0 address space For global address space throughput is at least 11 cycles 3 Load store multiple string instruction cycles are represen...

Page 278: ... arbitrate for address bus mastership Address transfer start These signals indicate that a bus master has begun a transaction on the address bus Address transfer These signals include the address bus and address parity signals They are used to transfer the address and to ensure the integrity of the transfer Transfer attribute These signals provide information about the type of transfer such as the...

Page 279: ...ache not supported in the MPC740 Interrupts resets These signals include the external interrupt signal checkstop signals and both soft reset and hard reset signals They are used to interrupt and under various conditions to reset the processor Processor status and control These signals are used to set the reservation coherency bit enable the time base and other functions They are also used in conju...

Page 280: ...BDIS Data Termination fA DRTRY TEA IiL2VDD L2AVDD Not supported in the MPC740 1 17 L2ADDR I6 0 1 64 L2DATA tHJ3 1 8 L2DP O 7 1 L2CE 1 L2WE 1 2 L2CLK OUT A B L2SYNC OUT 32 1 1 L2SYNC IN 4 1 L2ZZ 5 iNT 1 1 Siiifi 3 1 1 MCP 1 SRESET 1 1 1 RR ESET 1 MPC750 CKSTP IN 1 1 CKSTP OOT 1 1 RSRV 1 1 TBEN 1 1 TLBISYNC 1 1 QREQ 1 1 QACK 64 1 SYSCLK 8 4 PLL CFG 0 3 1 1 CLK OUT 1 5 JTAG COP 1 3 Factory Test 1 I I...

Page 281: ... MPC750 is not requesting the address bus The MPC750 may have no bus operation pending it may be parked or the ARTRY input was asserted on the previous bus clock cycle Timing Comments Assertion Occurs when the MPC750 is not parked and a bus transaction is needed This may occur even if the two possible pipeline accesses have occurred BR will also be asserted for one cycle during the execution of a ...

Page 282: ...1 Address Bus Arbitration Negated Indicates that the MPC750 is not using the address bus If ABB is negated during the bus clock cycle following a qualified bus grant the MPC750 did not accept mastership even if BR was asserted This can occur if a potential transaction is aborted internally before the transaction begins TIming Comments Assertion Occurs on the bus clock cycle following a qualified B...

Page 283: ...priate TT 0 4 signals it is also an implied data bus request for a memory transaction unless it is an address only operation Negated Indicates that no bus transaction is occurring during normal operation Timing Comments Assertion Coincides with the assertion ofABB Negation Occurs one bus clock cycle after TS is asserted High Impedance Coincides with the negation ofABB 7 2 2 1 2 Transfer Start TS I...

Page 284: ...lowing are the state meaning and timing comments for the A O 3l input signals State Meaning AssertedlNegated Represents the physical address of a snoop operation Timing Comments AssertionlNegation Must occur on the same bus clock cycle as the assertion ofTS is sampled by MPC750 only on this cycle 7 2 3 2 Address Bus Parity AP O 3 The address bus parity AP 0 3 signals are both input and output sign...

Page 285: ...For a detailed description of how these signals interact see Section 8 3 2 Address Transfer Note that some signal functions vary depending on whether the transaction is a memory access or an I O access 7 2 4 1 Transfer Type TT O 4 The transfer type TT 0 4 signals consist offive input output signals on the MPC750 For a complete description of TT 0 4 signals and for transfer type encodings see Table...

Page 286: ...d read read N A N A 0 0 0 0 1 lwarx Address only reservation set N A N A 0 0 1 0 1 ReservEid N A N A 0 1 0 0 1 tlbsync Address only N A N A 0 1 1 0 1 icbi Address only N A N A 1 X X 0 1 Reserved Single beat Caching inhibited 0 0 0 1 0 Write with flush Single beat write or write through write or burst store Burst Cast out or 0 0 1 1 0 Write with kill Burst nonGBL snoop copyback Single beat Caching ...

Page 287: ...Action on Hit Clean block Address only 0 0 0 0 0 N A Flush block Address only 0 0 1 0 0 N A sync Address only 0 1 0 0 0 N A Kill block Address only 0 1 1 0 0 Flush cancel reservation eieio Address onIy 1 0 0 0 0 N A External control word write Single beat write 1 0 1 0 0 N A TLB Invalidate Address only 1 1 0 0 0 N A External control word read Single beat read 1 1 1 0 0 N A Iwarx Address only 0 0 0...

Page 288: ...sertedlNegated For memory accesses these signals along with TBST indicate the data transfer size for the current bus operation as shown in Table 7 3 Table 8 3 shows how the transfer size signals are used with the address signals for aligned transfers Table 8 4 shows how the transfer size signals are used with the address signals for misaligned transfers Note that the MPC750 does not generate all p...

Page 289: ...Negation The same asA O 31 High Impedance The same as A 0 31 7 2 4 3 2 Transfer Burst TBST Input Following are the state meaning and timing comments for the TBST input signal State Meaning AssertedlNegated Used when snooping for single beat reads read with no intent to cache Timing Comments AssertionlNegation The same asA O 31 7 2 4 4 Cache Inhibit CI Output The cache inhibit CI signal is an outpu...

Page 290: ...tes that a transaction is global reflecting the setting of the M bit for the block or page that contains the address of the current transaction except in the case of copy back operations and instruction fetches which are nonglobal Negated Indicates that a transaction is not global Timing Comments AssertionlNegation The same asA 0 31 High Impedance The same as A 0 31 7 2 4 6 2 Global GBL Input Foll...

Page 291: ... signal is both an input and output signal on the MPC750 7 2 5 2 1 Address Retry ARTRY Output Following are the state meaning and timing comments for the ARTRY output signal State Meaning Asserted Indicates that the MPC750 detects a condition in which a snooped address tenure must be retried If the MPC750 needs to update memory as a result of the snoop that caused the retry the MPC750 asserts BR t...

Page 292: ...ata Bus Arbitration Signals Like the address bus arbitration signals data bus arbitration signals maintain an orderly process for determining data bus mastership Note that there is no data bus arbitration signal equivalent to the address bus arbitration signal BR bus request because except for address only transactions TS implies data bus requests For a detailed description on how these signals in...

Page 293: ...e DBWO and assume data bus ownership for the next pending read request Negation May occur any time after a qualified DBG and before the next assertion of DBG 7 2 6 3 Data Bus Busy DBB The data bus busy DBB signal is both an input and output signal on the MPC750 7 2 6 3 1 Data Bus Busy DBB Output Following are the state meaning and timing comments for the DBB output signal State Meaning Asserted In...

Page 294: ...ow DL See Table 7 4 for the data bus lane assignments Timing Comments The data bus is driven once for noncached transactions and four times for cache transactions bursts Table 7 4 Data Bus Lane Assignments Data Bus Signals Byte Lane DH Q 7 0 DH 8 15 1 DH 16 23 2 DH 24 31 3 DL O 7 4 DL 8 15 5 DL 16 23 6 DL 24 31 7 7 2 7 1 1 Data Bus DH O 31 DL O 31 Output Following are the state meaning and timing ...

Page 295: ...an odd number of bits including the parity bit are driven high The generation of parity is enabled through HIDO The signal assignments are listed in Table 7 5 Timing Comments AssertionlNegation The same as DL 0 31 High Impedance The same as DL O 31 Table 7 5 DP O 7 Signal Assignments Signal Name Signal Assignments DPO DH O 7 DP1 DH S 1S DP2 DH 16 23 DP3 DH 24 31 DP4 DL O 7 DPS DL S 15 DP6 DL 16 23...

Page 296: ...ignals interact see Section 8 4 4 Data Transfer Termination 7 2 8 1 Transfer Acknowledge TA Input Following are the state meaning and timing comments for the TA signaL State Meaning Asserted Indicates that a single beat data transfer completed successfully or that a data beat in a burst transfer completed successfully unless DRTRY is asserted on the next bus clock cycle Note that TA must be assert...

Page 297: ...mpled at the negation of HRESET if DRTRY is asserted no DRTRY mode is selected If DRTRY is negated at start up DRTRY is enabled 7 2 8 3 Transfer Error Acknowledge TEA Input Following are the state meaning and timing comments for the TEA signal State Meaning Asserted Indicates that a bus error occurred Causes a machine check exception and possibly causes the processor to enter checkstop state if ma...

Page 298: ...may be asserted asynchronously to the input clocks The INT input is level sensitive Negation Should not occur until interrupt is taken 7 2 9 2 System Management Interrupt SMI Input Following are the state meaning and timing comments for SMI State Meaning Asserted The MPC750 initiates a system management interrupt operation if the MSR EE is set otherwise the MPC750 ignores the exception condition T...

Page 299: ... has been reset Negated Indicates that normal operation should proceed See Section 8 7 2 Checkstops Timing Comments Assertion May occur at any time and may be asserted asynchronously to the input clocks Negation May occurany time after the CKSTP_OUT output signal has been asserted 7 2 9 5 Checkstop Output CKSTP_OUT Output Note that the CKSTP_OUT signal is an open drain type output and requires an ...

Page 300: ...mum of 255 clock cycles after the PLL lock time has been met Refer to the MPC750 hardware specifications for further timing comments Negation May occur any time after the minimum reset pulse width has been met This input has additional functionality in certain test modes 7 2 9 6 2 Soft Reset SRESET Input Following are the state meaning and timing comments for the SRESET signal State Meaning Assert...

Page 301: ...uiescent state and must continue snooping the bus Timing Comments AssertionlNegation May occur on any cycle following the assertion of QREQ and must be held asserted for at least one bus clock cycle 7 2 9 7 3 Reservation RSRV Output Following are the state meaning and timing comments for RSRV State Meaning Asserted Negated Represents the state of the reservation coherency bit in the reservation ad...

Page 302: ...ed as bit 16 Note that the L2 cache interface is not implemented in the MPC740 7 2 9 8 L2 Address L2ADDR 16 0 Output Following are the state meaning and timing comments for the L2 address output signals State Meaning AssertedlNegated Represents the address of the data to be transferred to the L2 cache The L2 address bus is configured with bit 0 as the least significant bit Address bit 14 determine...

Page 303: ...nsactions Odd parity means that an odd number of bits including the parity bit are driven high Note that parity bit 0 is associated with bits 0 7 byte lane 0 of the L2DATA bus Timing Comments AssertionlNegation The same as L2DATA 0 63 High Impedance The same as L2DATA 0 63 7 2 9 10 2 L2 Data Parity L2DP O 7 lnput Following are the state meaning and timing comments for the L2 parity input signals S...

Page 304: ...to the MPC750 hardware specifications for timing comments The L2CLK_OUTA signal is driven low during assertion of HRESET 7 2 9 14 L2 Clock Out B L2CLK_OUTB Output Following are the state meaning and timing comments for the L2CLK_OUTB signal State Meaning AssertedlNegated Clock output for L2 cache memory devices The L2CLK_OUTB signal is identical and synchronous with the L2CLK_OUTA signal and provi...

Page 305: ... enabled through the L2CR Timing Comments AssertionlNegation Occurs synchronously with the L2 clock when the MPC750 enters and exits the nap or sleep power modes after negation ofthis signal at least two L2 clock cycles will elapse before L2 cache operations resume The L2ZZ signal is driven low during assertion of HRESET 7 2 10 IEEE 1149 1a 1993 Interface Description The MPC750 has five dedicated ...

Page 306: ... CPU core to operate at an equal or greater frequency than the bus interface State Meaning AssertedlNegated The SYSCLK input is the primary clock input for the MPC750 and represents the bus clock frequency for MPC750 bus operation Internally the MPC750 may be operating at an integer or half integer multiple of the bus clock frequency Timing Comments Duty cycle Refer to the MPC750 hardware specific...

Page 307: ...D signals provide the supply voltage connection for the processor core e OVDD The OVDD signals provide the supply voltage connection for the system interface drivers L2VDD The L2VDD signals provide the supply voltage connection for the L2 cache interface drivers These power supply signals are isolated from the VDD and OVDD power supply signals These signals are not implemented on the MPC740 AVDD T...

Page 308: ...e memory system into the instruction unit where they are dispatched to the execution units at a peak rate of two instructions per clock Conversely load and store instructions explicitly specify the movement of operands to and from the integer and floating point register files and the memory system When the MPC750 encounters an instruction or data access it calculates the logical address effective ...

Page 309: ...eat operations global memory operations that are snooped and atomic memory operations for example and address retry activity for example when a snooped read access hits a modified line in the cache Since the MPC750 data cache tags are single ported simultaneous load or store and snoop accesses cause resource contention Snoop accesses have the highest priority and are given first access to the tags...

Page 310: ...ion II Reservation Station I Reservation Station Reservation Station I GPR File 2 Entry FPR File Rename Buffers Rename Buffers 6 6 ISystem RegisterI I I 32 Bit load Store Unit 64 Bit bh 64 Bit Floating Point Integer Unill integer Unil2 Unit Unit 0 G ido J I EA Calculation Store Queue I FPSCR I I t 32 Bit I 1 3 Bit C 3 1 1 L PA EA 1 t Completion Unit 60x Bus Interface Unit I I DataMMU 64 Bit Instru...

Page 311: ...ags and the data or instructions are forwarded from the L2 to the Ll cache if there is a cache hit or are forwarded on to the bus interface unit if there is an L2 cache miss or if the address being accessed is from a page marked as caching inhibited Burst read accesses that miss in the L2 cache initiate a load operation from the bus interface As the load operation transfers data to the L1 cache th...

Page 312: ...rams that illustrate how the signals interact A collection of more general timing diagrams are included as examples of typical bus operations Figure 8 2 is a legend of the conventions used in the timing diagrams This is a synchronous interface all MPC750 input signals are sampled and output signals are driven on the rising edge of the bus clock cycle see the MPC750 hardware specifications for exac...

Page 313: ...cess Protocol Memory accesses are divided into address and data tenures Each tenure has three phases bus arbitration transfer and termination The MPC750 also supports address only transactions Note that address and data tenures can overlap as shown in Figure 8 3 Figure 8 3 shows that the address and data tenures are distinct from one another and that both consist of three phases arbitration transf...

Page 314: ...e data tenure the MPC750 arbitrates for mastership of the data bus Transfer After the MPC750 is the data bus master it samples the data bus for read operations or drives the data bus for write operations The data parity and data parity error signals ensure the integrity of the data transfer Termination Data termination signals are required after each data beat in a data transfer Note that in a sin...

Page 315: ...ation signals 8 8 DBG data bus grant Indicates that the MPC750 may with the proper qualification assume mastership of the data bus A qualified data bus grant occurs when DBG is asserted while DBB DRTRY and ARTRY are negated The DBB signal is driven by the current bus master DRTRY is only driven from the bus and ARTRY is from the bus but only for the address bus tenure associated with the current d...

Page 316: ... granting mastership ofthe address bus to the next requesting master before the current data bus tenure has completed Two address tenures can occur before the current data bus tenure completes The MPC750 can pipeline its own transactions to a depth of one level intraprocessor pipelining however the MPC750 bus protocol does not constrain the maximum number of levels of pipelining that can occur on ...

Page 317: ...s address bus mastership by asserting ABB when it receives a qualified bus grant 1 o Logical Bus Clock foIlE JlE J l Figure 8 4 Address Bus Arbitration External arbiters must allow only one device at a time to be the address bus master Implementations in which no other device can be a master BG can be grounded always asserted to continually grant mastership of the address bus to the MPC750 Ifthe M...

Page 318: ...ooping if the MPC750 asserts BR to perform a replacement copy back operation another device can invalidate that line before the MPC750 is granted mastership of the bus Once the MPC750 is granted the bus it no longer needs to perform the copy back operation therefore the MPC750 does not assert ABB and does not use the bus for the copy back operation Note that the MPC750 asserts BR for at least one ...

Page 319: ...ls transfer type TT 0 4 transfer size TSIZ O 2 transfer burst TBST cache inhibit CI write through WT and global GBL Figure 8 6 shows that the timing for all of these signals except TS is identical All of the address transfer and address transfer attribute signals are combined into the ADDR grouping in Figure 8 6 The TS signal indicates that the MPC750 has begun an address transfer and that the add...

Page 320: ...everal encoded signals such as the transfer type TT 0 4 signals transfer burst TBST signal transfer size TSIZ 0 2 signals write through WT and cache inhibit CI Section 7 2 4 Address Transfer Attribute Signals describes the encodings for the address transfer attribute signals 8 3 2 2 1 Transfer Type TT 0 4 Signals Snooping logic should fully decode the transfer type signals if the GBL signal is ass...

Page 321: ...saction with a transfer size of 5 bytes 6 bytes or 7 bytes 8 3 2 2 3 Write Through WT Signal The MPC750 provides the WT signal to indicate a write through operation as determined by the WIM bit settings during address translation by the MMU The WT signal is also asserted for burst writes due to the execution of the debf and debst instructions and snoop push operations The WT signal is deasserted f...

Page 322: ...W3 Second data beat DW1 DW2 DW3 DWO Third data beat DW2 DW3 DWO DW1 Fourth data beat DW3 DWO DW1 DW2 Note A 29 31 are always ObOOO for burst transfers by the MPC750 8 3 2 4 Effect of Alignment in Data Transfers Table 8 3 lists the aligned transfers that can occur on the MPC750 bus These are transfers in which the data is aligned to an address that is an integral multiple of the size of the data Fo...

Page 323: ...perations hit in the primary cache or generate burst memory operations if they miss the MPC750 interface supports misaligned transfers within a word 32 bit aligned boundary as shown in Table 8 4 Note that the 4 byte transfer in Table 8 4 is only one example ofmisalignment As long as the attempted transfer does not cross a word boundary the MPC750 can transfer the data on the misaligned address for...

Page 324: ...4 bytes If the eciwx or ecowx instruction is misaligned and crosses any word boundary the MPC750 will generate an alignment exception 8 3 3 Address Transfer Termination The address tenure of a bus operation is terminated when completed with the assertion of AACK or retried with the assertion of ARTRY The MPC750 does not terminate the address transfer until the AACK address acknowledge input is ass...

Page 325: ...RTRY is received up to or on the bus cycle following the first or only assertion ofTA for the data tenure the MPC750 ignores the first data beat and if it is a load operation does not forward data internally to the cache and execution units If ARTRY is asserted after the first or only assertion of TA improper operation of the bus interface may result During the clock of a qualified ARTRY the MPC75...

Page 326: ...he combination of TS and IT O 4 provides information about the data bus request to external logic The TS signal is an implied data bus request from the MPC750 the arbiter must qualify TS with the transfer type IT encodings to determine if the current address transfer is an address only operation which does not require a data bus transfer see Figure 8 7 If the data bus is needed the arbiter grants ...

Page 327: ...onally the memory system can control data tenure scheduling directly with DBG However it is possible to ignore the DBB signal in the system if the DBB input is not used as the final data bus allocation control between data bus masters and if the memory system can track the start and end of the data tenure If DBB is not used to signal the end of a data tenure DBG is only asserted to the next bus ma...

Page 328: ...e DR and DL signals form a 64 bit data path for read and write operations The MPC750 transfers data in either single or four beat burst transfers Single beat operations can transfer from 1 to 8 bytes at a time and can be misaligned see Section 8 3 2 4 Effect of Alignment in Data Transfers Burst operations always transfer eight words and are aligned on eight word address boundaries Burst transfers ...

Page 329: ...egate DRTRY on that clock This is to prevent a potential momentary data bus conflict if a write access begins on the following cycle The TEA signal is used to signal a nonrecoverable error during the data transaction It may be asserted on any cycle during Di313 or on the cycle after a qualified fA during a read operation except when no DRTRY mode is selected where no DRTRY mode cancels checking th...

Page 330: ... __ Ji Figure 8 9 Normal Single Beat Read Termination The DRTRY signal is not sampled during data writes as shown in Figure 8 10 o 2 3 AACK Figure 8 10 Normal Single Beat Write Termination Chapter 8 System Interface Operation 8 23 ...

Page 331: ... and that the processor must wait for the negation of DRTRY before forwarding data to the processor see Figure 8 12 Thus a data beat can be terminated by a predicted branch with fA and then one bus clock cycle later confirmed with the negation of DRTRY The DRTRY signal is valid only for read transactions TA must be asserted on the bus clock cycle before the first bus clock cycle of the assertion o...

Page 332: ...eed until bus clock cycle 4 when the TA is reasserted 2 3 4 5 6 7 8 9 L I 18 _ ___ _ _ _ _ _ _ _ _ J Figure 8 13 Read Burst with TA Wait States and DRTRY Note that DRTRY is useful for systems that implement predicted forwarding of data such as those with direct mapped third level caches where hit miss is determined on the following bus clock cycle or for parity or ECC checked memory systems Note t...

Page 333: ...nd DRTRY assertion for reads delay termination of individual data beats Eventually however the system must either terminate the transaction or assert the TEA signal For this reason care must be taken to check for the end of physical memory and the location of certain system facilities to avoid memory accesses that result in the assertion of TEA Note that TEA generates a machine check exception dep...

Page 334: ...d with the TS is compared against the data cache tags Snooping completes if no hit is detected If however the address hits in the cache the MPC750 reacts according to the MEl protocol shown in Figure 8 14 assuming the WIM bits are set to write back caching allowed and coherency enforced modes WIM 001 SH Snoop Hit RH Read Hit WH Write Hit WM Write Miss RM Read Miss BUS TRANSACTIONS Snoop Push CD Ca...

Page 335: ...elining the overall throughput is not affected unless the data bus latency causes the third address tenure to be delayed Note that all bidirectional signals are three stated between bus tenures 8 28 I 1 2 3 4 5 6 7 I 8 9 10 11 12 I 1 _ 11 I LU A Q 31 CP U A CPUA C C PU AC TT O 4 R ea d Read t C jR ea d T8ST ARTRY M 0 0 o j lt iii i it ii b o 2 O i ii OBB LU LU LU 0 0 63 1 0 T T C J T T TA fj iiX o...

Page 336: ... tenures I 1 2 I 3 I 4 5 6 7 I 8 9 10 11 12 BR 7 7 BGh I 7 ABB fT fT I TS L W i I L0 A 0 31 i CPUA H CPU A H CPU A TT 0 4 SBW r ssw M ssw TBST GBL AACK W UJ U J ARTRY OBG I I I OBB L0 L0 LlJ 0 0 63 TA I I I ORTRY TEA I 1 2 I 3 I 4 5 6 7 I 8 I 9 10 11 12 Figure 8 16 Fastest Single Beat Writes Chapter 8 System Interface Operation 8 29 ...

Page 337: ...8 17 can occur if the second access is not another load for example an instruction fetch 2 3 I 4 5 6 7 I 8 9 I 10 11 12 13 I 14 I I I I 1 1 I 1 BRI 1 CV 1 C0 I 1 BG Ai o 01 i I o Ail oio i dW ABB I r I r jr I 1 I r i I i 1 TS A 0 31 1 1 CPU A CPU A CPU A I I 1 1 1 1 TT O 4 1 1 Read Read Read 1 1 1 1 1 1 1 1 TBST 1 1 1 1 1 1 ill3I ji i s l W 1 If ll Ii Yii i Vli iii AACK y ARTRyl 1 OBBI 1 0 0 63 1 ...

Page 338: ...cess is not delayed DRTRY is valid only for read operations I 1 2 I 3 I 4 I 5 6 7 I 8 9 I 10 11 12 BR J J BG n Li w J t dWt 1i Df n 6 H sF4S 1W I I I I I im 0 _ 1 LLJ LLJ LLJ A Q 31 r C C PU A H _CP_U_A J8c cP U A f j TT O 4 C S BWCJ SBW i C SB W i TBST GBl j rl j fJ 08 0 1 Irj i l iJ 10 l i J AACK i r r UJ ARTRY DBG 4 fj t i t ii1 i 1 J E 1 1 J i 0 L o tii6 a i f W 0 h 1 DBB 1 i fT U D Q 63 C o u...

Page 339: ...f DRTRY on the third data beat The address for the third transfer is delayed until the first transfer completes 8 32 1 1 1 2 1 3 14 15 1 6 1 7 1 8 1 9 110 111 112 113 114 115116117 118 119 120 1 BR tuJ iL j i 1 i I I I I A 0 31 TT Q 4 fBSl G8 jltl I f iNj AACK ARTRY l j W CPUA Read I I I rh t j i Hm I I I DBG i f f t01 0 i gr i i 4iv t 6 1 J DBB 0 0 63 In 0 TA Wil l ij DRTRY TEA rn r G 0 t t r J 1...

Page 340: ... The TEA signal truncates the burst write transfer on the third data beat The MPC750 eventually causes an exception to be taken on the TEA event 1112131415161718191101111121131141151161171 A Q 31 TT O 4 TBST AACK OBG 8 OBB l o I l 0 0 63 i n yJr 2 I 3 TA 0 I JiG O c j I I JJ 1112131415161718191101111121131141151161171 Figure 8 20 Use of Transfer Error Acknowledge TEA Chapter 8 System Interface Ope...

Page 341: ...ta can no longer be cancelled the cycle after it is acknowledged by an assertion ofTA Data is immediately forwarded to the CPU internally and any attempt at late cancellation by the system may cause improper operation by the MPC750 When the MPC750 is following normal bus protocol data may be cancelled the bus cycle after fA by either of two means late cancellation by DRTRY or late cancellation by ...

Page 342: ...RESET hard reset The HRESET signal is used for power on reset sequences or for situations in which the MPC7SO must go through the entire cold start sequence of internal hardware initializations SRESET soft reset The soft reset input provides warm reset capability This input can be used to avoid forcing the MPC7S0 to complete the cold start sequence When either reset input is negated the processor ...

Page 343: ...eflects the status of the reservation coherency bit in the reservation address register see Chapter 3 Ll Instruction and Data Cache Operation for more information For information about timing see Section 7 2 9 7 3 Reservation RSRV Output 8 8 2 TlBISYNC Input The TLBISYNC input allows for the hardware synchronization of changes to MMU tables when the MPC750 and another DMA master share the same MMU...

Page 344: ... 21 For more information refer to IEEE Standard Test Access Port and Boundary Scan Architecture IEEE STD 1149 1a 1993 TOI Test Data Input TMS Test Mode Select l TCK Test Clock Input j TOO Test Data Output l TRST Test Reset Figure 8 21 IEEE 1149 1a 1993 Compliant Boundary Scan Interface 8 10 USing Data Bus Write Only The MPC750 supports split transaction pipelined transactions It supports a limited...

Page 345: ...d the read transaction special care should be used when using the enveloped write feature It is envisioned that most system implementations will not need this capability for these applications DBWO should remain negated In systems where this capability is needed DBWO should be asserted under the following scenario 1 The MPC750 initiates a read transaction either single beat or burst by completing ...

Page 346: ...peration may be the highest priority write but more than one may be queued Because more than one write may be in the write queue when DBG is asserted for the write address more than one data bus write may be enveloped by a pending data bus read The arbiter must monitor bus operations and coordinate the various masters and slaves with respect to the use of the data bus when DBWO is used Individual ...

Page 347: ...8 40 MPC750 RISC Microprocessor User s Manual ...

Page 348: ...es depending on the L2 cache size Ifthe L2 cache is configured for 256 Kbytes or 512 Kbytes of external SRAM the tags are configured for two sectors per L2 cache block The L2 tags are configured for four sectors per L2 cache block when 1 Mbyte of external SRAM is used Each sector 32 byte L1 cache block in the L2 cache has its own valid and modified bits The L2 cache control register L2CR allows co...

Page 349: ...ads should be presented on each L2 interface signal Figure 9 1 Typical 1 Mbyte L2 Cache Configuration 9 1 1 L2 Cache Operation The MPC750 s L2 cache is a combined instruction and data cache that receives memory requests from both LI instruction and data caches independently The LI requests are generally the result of instruction fetch misses data load or store misses write through operations or ca...

Page 350: ...yback are written only to the L2 cache and the L2 cache sector is marked modified Designers should note that during burst transfers into and out of the L2 cache SRAM array an address is generated by the MPC750 for each data beat Ifthe L2 cache is configured as write through the L2 sector is marked unmodified and the write is forwarded to the 60x bus If the L1 castout requires a new L2 tag entry to...

Page 351: ...orm a sector invalidation and or push from the L2 cache to the 60x bus as required If the debf and debst instructions do not cause a sector push from the L2 cache they are forwarded to the 60xbus interface for address only broadcast if HIDO ABE is set to 1 The debi instruction is always forwarded to the L2 cache and causes a segmentinvalidation if a hit occurs The debi instruction is also forwarde...

Page 352: ... RAMs that support the ZZ function This bit should not be set when the MPC750 is in nap mode and snooping is being performed through deassertion of QACK 12 L2WT L2 write through Setting L2WT selects write through mode rather than the default copy back mode so all writes to the L2 cache also write through to the 60x bus 13 L2TS L2 test support Setting L2TS causes cache block pushes from the L1 data...

Page 353: ...ly performed by the assertion ofHRESET signal Disable L2 cache by clearing L2 CR L2E Set the L2CR L2CLK bits to the desired clock divider setting Setting a nonzero value automatically enables the DLL All other L2 cache configuration bits should be set to properly configure the L2 cache interface for the SRAM type size and interface timing required Wait for the L2 DLL to achieve phase lock This can...

Page 354: ...hods In the course of system power up testing may be required to verify the proper operation of the L2 tag memory external SRAM and overall L2 cache system The following sections describe the MPC750 s features and methods for testing the L2 cache The L2 cache address space should be marked as guarded G 1 so spurious load operations are not forwarded to the 60x bus interface before branch resolutio...

Page 355: ...olds a sequential range of addresses disable the Ll data cache and execute a series of single beat load and store operations employing a variety of bit patterns to test for stuck bits and pattern sensitivities in the L2 cache SRAM The performance monitor can be used to verify whether the number of L2 cache hits or misses corresponds to the tests performed Test the L2 cache tag memory by enabling t...

Page 356: ... interface The timing diagrams illustrate the best case logical ideal non AC timing accurate interface operations For proper interface operation the designer must select SRAMs that support the signal sequencing illustrated in the timing diagrams Designers should also note that during burst transfers into and out of the L2 cache SRAM array an address is generated by the MPC750 for each data beat Th...

Page 357: ...for the last read Figure 9 2 Burst Read Write Read L2 Cache Access Flow Through Figure 9 3 shows a burst read modify write memory access sequence when the L2 cache interface is configured with flow through burst SRAM SRAMClk L2WE SRAMAddress SRAMMemory SRAMData I Note Rxlr indicates where an extra read cycle is signaled to keep the burst RAM driving the data bus for the last read Figure 9 3 Burst ...

Page 358: ...nto the data bus This causes initial read accesses by the pipelined burst SRAMs to occur one cycle later than flow through burst SRAMs but the L2 bus frequencies supported can be higher Note that the MPC750 s L2 cache interface requires the use of single cycle deselect pipelined burst SRAM for proper operation Figure 9 5 shows a burst read write read memory access sequence when the L2 cache interf...

Page 359: ...k L2WE SRAMAddress SRAMMemory SRAMData I Notes Rdrv indicates where some burst RAMs may begin driving the data bus Rxtr indicates where an extra read cycle is signaled to keep the burst RAM driving the data bus for the last read Figure 9 7 Burst Read Write Write L2 Cache Access Pipelined 9 1 7 3 Late Write SRAM Late write SRAMs offer improved performance when compared to pipelined burst SRAMs by n...

Page 360: ...t was queued in the late write RAM Figure 9 8 Burst Read Write Read L2 Cache Access Late Write SRAM Figure 9 9 shows a burst read modify write memory access sequence when the L2 cache interface is configured with late write SRAM SRAMClk L2CE L2WE SRAMAddress I I I I I SRAMMemory RO R1 R2 R3 I I I I SRAMData I RO R1 R2 Note WQ is the last previous write that was queued in the late write RAM Figure ...

Page 361: ...he interface is configured with late write SRAM SRAMClk L2CE L2WE SRAMAddress SRAMMemory SRAMData Note WQ is the last previous write that was queued in the late write RAM Figure 9 10 Burst Read Write Write L2 Cache Access Late Write SRAM 9 14 MPC750 RISC Microprocessor User s Manual ...

Page 362: ...eliminates its power consumption The operation of DPM is completely transparent to software or any external hardware Dynamic power management is enabled by setting HIDO DPM to l 10 2 Programmable Power Modes The MPC750 provides four programmable power states full power doze nap and sleep Software selects these modes by setting one and only one of the three power saving mode bits in the HIDO regist...

Page 363: ...rrupts in the architecture specification 10 2 1 Power Management Modes The following sections describe the characteristics of the MPC750 s power management modes the requirements for entering and exiting the various modes and the system capabilities provided by the MPC750 while the power management modes are active 10 2 1 1 Full Power Mode with DPM Disabled Full power mode with DPM disabled is sel...

Page 364: ... handshake sequence using the quiesce request QREQ and quiesce acknowledge QACK signals The MPC750 asserts the QREQ signal to indicate that it is ready to disable bus snooping When the system has ensured that snooping is no longer necessary it will assert QACK and the MPC750 will enter the nap mode If the system determines that a bus snoop cycle is required QACK is deasserted to the MPC750 for at ...

Page 365: ...l into a static state does not disable the MPC750 s PLL which will continue to operate internally at an undefined frequency unless placed in PLL bypass mode Additionally if the PLL is not disabled the L2 cache interface DLL will remain locked and the L2CLK_OUTA and L2CLK_OUTB signals will remain active The DLL is disabled by clearing the L2CR L2E bit to O Due to the fully static design of the MPC7...

Page 366: ...r example INT or SMI Reconfigure DLL wait for DLL relock 640 L2 clock cycles and re enable L2 cache through the L2CR 10 2 2 Power Management Software Considerations Since the MPC750 is a dual issue processor with out of order execution capability care must be taken in how the power management mode is entered Furthermore nap and sleep modes require all outstanding bus operations to be completed bef...

Page 367: ...designer an efficient means of monitoring junction temperature through the incorporation of an on chip thennal sensor and programmable control logic to enable a thennal management implementation tightly coupled to the processor for improved perfonnance and reliability 10 3 1 Thermal Assist Unit Overview The on chip thennal assist unit TAU is composed of a thermal sensor a digital to analog convert...

Page 368: ... result of the temperature comparison to set TIN If TID is cleared to 0 TIN is set and an interrupt occurs if the junction temperature exceeds the threshold If TID is set to 1 TIN is set and an interrupt is indicated if the junction temperature is below the threshold 30 TIE Thermal management interrupt enable Enables assertion of the thermal management interrupt Signal The thermal management inter...

Page 369: ...ld The THRM3 SITV setting determines the number of processor clock cycles between input to the DAC and sampling of the comparator output accordingly the use of a value smaller than recommended in the THRM3 SITV field can cause inaccuracies in the sensed temperature If the junction temperature does not cross the programmed threshold the THRMn TIN bit is cleared to 0 to indicate that no interrupt is...

Page 370: ...gement interrupt is generated if TIE 1 Note 1The TIN and TIV bits are read only status bits 10 3 2 2 TAU Dual Threshold Mode The configuration and operation of the TAU s dual threshold mode is similar to single threshold mode except both THRMI and THRM2 are configured with desired threshold and TID values and the TIE and V bits are set to 1 When the THRM3 E bit is set to 1 to enable temperature me...

Page 371: ...ing sleep mode with SYSCLK disabled the TAU should be configured to disable thermal management interrupts to avoid an unwanted thermal management interrupt when the SYSCLK input signal is restored 10 4 Instruction Cache Throttling The MPC750 provides an instruction cache throttling mechanism to effectively reduce the instruction execution rate without the complexity and overhead of dynamic clock c...

Page 372: ...ts Name Description 23 30 FI Instruction forwarding interval expressed in processor clocks OxOO O clock cycle Ox01 1 clock cycle OxFF 255 clock cycles 31 E Cache throttling enable 0 Disable instruction cache throttling 1 Enable instruction cache throttling Chapter 10 Power and Thermal Management 10 11 ...

Page 373: ...10 12 MPC750 RISC Microprocessor User s Manual ...

Page 374: ...essor architecture the detailed behavior of the MPC750 s structure must be known and understood in many software environments Some environments may not be easily characterized by a benchmark or trace To help system developers bring up and debug their systems The performance monitor uses the following MPC750 specific special purpose registers SPRs The performance monitor counter registers PMCI PMC4...

Page 375: ... one of the performance monitor counter registers PMCI PMC4 shown in Figure 11 3 A counter is considered to have overflowed when its most significant bit is set A performance monitor interrupt may also be caused by the flipping from 0 to 1ofcertain bits in the time base register which provides a way to generate a time reference based interrupt Although the interrupt signal condition may occur with...

Page 376: ...upervisor 936 Ob1110101000 UMMCRO User read only 937 Ob1110101001 UPMC1 User read only 938 Ob1110101010 UPMC2 User read only 939 Ob1110101011 USIA User read only 940 Ob1110101100 UMMCR1 User read only 941 Ob1110101101 UPMC3 User read only 942 Ob1110101110 UPMC4 User read only 11 2 1 Performance Monitor Registers This section describes the registers used by the performance monitor 11 2 1 1 Monitor ...

Page 377: ...MCn counters are not changed by hardware 4 DMR Disables counting while MSR PM is zero 0 The PMCn counters can be changed by hardware 1 If MSR PM is cleared the PMCn counters are not changed by hardware 5 ENINT Enables performance monitor interrupt signaling 0 Interrupt signaling is disabled 1 Interrupt signaling is enabled Cleared by hardware when a performance monitor interrupt is signaled To re ...

Page 378: ...COUNT 0 Disable PMC2 PMC4 interrupt signaling due to PMC2 PMC4 counter overflow 1 Enable PMC2 PMC4 interrupt signaling due to PMC2 PMC4 counter overflow 18 PMCTRIGGER Can be used to trigger counting of PMC2 PMC4 after PMC1 has overflowed or after a performance monitor interrupt is signaled 0 Enable PMC2 PMC4 counting 1 Disable PMC2 PMC4 counting until either PMC1 0 1 or a performance monitor inter...

Page 379: ...er Registers PMC1 PMC4 PMCI PMC4 shown in Figure 11 3 are 32 bit counters that can be programmed to generate interrupt signals when they overflow Counter Value o 1 31 Figure 11 3 Performance Monitor Counter Registers PMC1 PMC4 The bits contained in the PMC registers are described in Table 11 4 Table 11 4 PMCn Bit Settings Bits Name Description 0 OV Overflow When this bit is set it indicates this c...

Page 380: ...s per cycle 0000101 Number of eieio instructions completed 0000110 Number of cycles spent performing table search operations for the ITLB 0000111 Number of accesses that hit the L2 0001000 Number of valid instruction EAs delivered to the memory subsystem 0001001 Number of times the address of an instruction being completed matches the address in the IABR 0001010 Number of loads that miss the L1 wi...

Page 381: ...leted instructions not including folded branches 00011 Number of TBL bit transitions from ato 1 of specified bits in time base lower register Bits are specified through RTCSELECT MMRCO 7 8 a 47 1 51 2 55 3 63 00100 Number of instructions dispatched 0 1 or 2 per cycle 00101 Number of L1 data cache misses 00110 Number of DTLB misses 00111 Number of L2 data misses 01000 Number of taken branches inclu...

Page 382: ...1 Reserved May be used in a later revision 01000 Number of mispredicted branches 01001 Number of transitions between marked and unmarked processes while in user mode That is the number of MSR PM toggles while the processor is in supervisor mode 01010 Number of store conditional instructions completed with reservation intact 01011 Number of completed sync instructions 01100 Number of snoop request ...

Page 383: ...ndition The SIA is shown in Figure 11 4 Instruction Address o 31 Figure 11 4 Sampled instruction Address Registers SIA If the performance monitor interrupt is triggered by a threshold event the SIA contains the address of the exact instruction called the sampled instruction that caused the counter to overflow If the performance monitor interrupt was caused by something besides a threshold event th...

Page 384: ...ng is enabled counting is enabled The following are states that can be monitored Supervisor only User only Marked and user only Not marked and user only Marked and supervisor only Not marked and supervisor only Marked only Not marked only In addition one of two unconditional counting modes may be specified Counting is unconditionally enabled regardless of the states of MSR PM and MSR PR This can b...

Page 385: ...be reference events These are as follows OOOOO Register holds current value 00001 Number of processor cycles 00010 Number of completed instructions not including folded branches 00011 Number ofTBL bit transitions from 0 to 1 of specified bits in time base lower register Bits are specified through RTCSELECT MMCRO 7 8 0 47 1 51 2 55 3 63 001DO Number of instructions dispatched 0 1 or 2 per cycle Som...

Page 386: ...structions Note that split fields that represent the concatenation of sequences from left to right are shown in lowercase For more information refer to Chapter 8 Instruction Set in The Programming Environments Manual A 1 Instructions Sorted by Mnemonic Table A I lists the instructions implemented in the PowerPC architecture in alphabetical order by mnemonic Key Reserved bits Table A 1 Complete Ins...

Page 387: ... cntlzdx 1 31 S A III 58 IRe cntlzwx 31 S A 26 IRe erand 19 erbD erbA erbB 257 erandc 19 erbD erbA erbB 129 ereqv 19 erbD erbA erbB 289 ernand 19 erbD erbA erbB 225 ernor 19 erbD erbA erbB 33 eror 19 erbD erbA erbB 449 erore 19 erbD erbA crbB 417 crxor 19 crbD erbA erbB 193 deba 2 7 31 A B 758 debf 31 A B 86 debi 3 31 A B 470 debst 31 A B 54 debt 31 A B 278 debtst 31 A B 246 jl debz 31 A B 1014 It...

Page 388: ...1 s 31 s 63 D 63 D 59 D fcfidx 1 63 fum D B 32 1 fum D B o fctidx 1 63 B 814 fctidzx 1 63 D B 815 63 D B 14 63 D 63 D 59 D A B 63 D A B 59 D A B c 29 63 D 72 63 D c 28 59 D c 28 63 D c 25 59 D c 25 63 D 136 63 D 40 63 D A B c 31 fnmaddsx 59 D A B c 31 63 D A B c 30 59 D fresx 2 59 D Appendix A PowerPC Instruction Set Listings A 3 ...

Page 389: ... D A B 119 Ibzx 31 D A B 87 Id 1 58 D A ds Idarx 1 31 D A B 84 Idu 1 58 D A ds Idux 1 31 D A B 53 Idx 1 31 D A B 21 ltd 50 D A d Ifdu 51 D A d Ifdux 31 D A B 631 Ifdx 31 D A B 599 Ifs 48 D A d Ifsu 49 D A d Ifsux 31 D A B 567 Ifsx 31 D A B 535 Iha 42 D A d Ihau 43 D A d Ihaux 31 D A B 375 Ihax 31 D A B 343 Ihbrx 31 D A B 790 1hz 40 D A d Ihzu 41 D A d A 4 MPC750 RISC Microprocessor User s Manual ...

Page 390: ...rfD 00 crfS 0 0 o O OO 64 0 mcrxr 31 crfD 00 OQaoo 1 0 9oo 512 k mfcr 31 0 0000 0 0 0001 0 1 19 mffsx 63 0 oqo6 OOOl lo 583 Rc mfmsr 3 31 0 O OOOi Ii OOOO 83 0 mfspr 5 31 0 spr 339 a mfsr 3 6 31 0 01 SR DOOOB 595 0 mfsrin 3 6 31 0 op060 B 659 0 mftb 31 0 tbr 371 0 mtcrf 31 S 0 1 CRM f 144 mtfsbOx 63 crbD o o aH o o ao 70 Rc I mtfsb1x 63 crbD OO OQ OQOO i 38 Rc mtfsfx 63 1 0 1 FM r B 711 Rc mtfsfix...

Page 391: ...llwx 31 0 A 235 nandx 31 S A 476 negx 31 0 A 104 norx 31 S A B 124 orx 31 S A B 444 orcx 31 S A B 412 ori 24 S A UIMM oris 25 S A UIMM rfi 3 6 19 50 rfid 1 3 19 18 rldclx 1 30 S A B mb 8 rldcrx 1 30 S A B me rldicx 1 30 S A sh mb 2 rldiclx 1 30 S A sh mb 0 rldicrx 1 30 S A sh me rldimix 1 30 S A sh mb 3 rlwimix 20 S A SH MB ME 21 S A SH MB ME 23 sc 17 slbia 1 2 3 31 slbie 1 2 3 31 434 sldx 1 31 B ...

Page 392: ... S 31 S 31 S 31 S 31 S 38 S 39 S 31 S 31 S 62 S 31 S 62 S 31 S 31 S 54 S 55 S 31 S 31 S 31 S 52 S 53 S 31 S 31 S 44 S 31 S 45 S 31 S 31 S 47 S 31 S 31 S 36 S Appendix A PowerPC Instruction Set Listings A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B 794 Rc sh 413 ISh Rc B 792 Rc SH 824 Rc B 539 Rc B 536 Rc d d B 247 0 B 215 0 ds I 0 B 214 1 ds 1 1 B 181 6 B 149 in d d B 759 10 ...

Page 393: ...1 1 tw 31 twi 03 TO 31 S xori 26 S xoris 27 S Notes 1 64 bit instruction 2 Optional instruction 3 Supervisor level instruction 4 Load store string multiple instruction 5 Supervisor and user level instruction 6 Optional 64 bit bridge instruction A B 662 A B 150 A d A B 183 A B 151 A B 40 A B 8 A B 136 A SIMM 232 200 598 68 SIMM 370 306 566 4 A SIMM A B 316 A UIMM A UIMM 7 32 bit instruction not imp...

Page 394: ...M 001011 crfD L A SIMM 001100 0 A SIMM 001101 0 A SIMM 001110 0 A SIMM 001 1 11 0 A SIMM 010000 BO BI BD AA LK 010001 l ti Q iii i i Q Ie 0QQQOD 0 HiO OOQ 1 0 010010 LI AA LK 01001 1 crfD QiQ crfS log Ic OOQO 1 0000000000 0 010011 BO BI 1 Q QO q 0000010000 LK 010011 I v i ii i 9i O O l i 1 DOqo 0000010010 0 010011 crbD crbA crbB 0000100001 i r q O i Q Q OQ O 0 01001 1 0000110010 01001 1 crbD crbA ...

Page 395: ...rldcrx 1 011 1 10 S A B me 01001 Rc cmp 011 1 1 1 crfD t 1 L A B 0000000000 o tw 01 1 1 1 1 TO A B 0000000100 r subfcx 011111 D A B PE 0000001000 Rc CC mUlhdux 1 011111 D A B O c 0000001001 Rc addcx 011111 D A B OE 0000001010 Rc mulhwux 011111 D A B 1 0 0000001011 Rc mfcr 011111 D l iip g Jil qfKl 0000010011 i Iwarx 011111 D A B 0000010100 t Idx 1 011111 D A B 0000010101 O Iwzx slwx 011111 D A B 0...

Page 396: ... 0000110111 0 S A 00000 0000111010 Rc S A B 0000111100 Rc TO A B 0001000100 0 D A B a 0001001001 Rc D A B a 0001001011 Rc S 0 1 SR 00000 0001010010 a D 00000 00000 0001010011 a D A B 0001010100 0 00000 A B 0001010110 0 D A B 0001010111 a D A 00000 OE 0001101000 Rc S 00000 B 0001110010 D A B 0001110111 0 S A B 0001111100 Rc D A B OE 0010001000 Rc D A B OE 0010001010 Rc S oj CRM 1 0 0010010000 0 S 0...

Page 397: ...5 011111 D spr 0101010011 Iwax 1 011111 D A B 0101010101 I Ihax tibia 2 4 7 mftb 011111 D 0101010111 I P 011111 F dddo I A o 0101110010 0 i i o1 1 1 1 1 D tbr 0101110011 R Iwaux 1 o1 1 1 1 1 0 A B 0101110101 R Ihaux o1 1 1 1 1 D A B 0101110111 L sthx 011111 S A B 0110010111 19 orex 011111 s A B 0110011100 Rc sradix 1 011111 S A sh 1100111011 ISh Rc slbie 1 2 4 011111 C O A i p i B 0110110010 eeowx...

Page 398: ...riD 1 00 00000 D A D A D A S A S A I 00000 00000 D A D oj SR D A 000 00 00000 D A D A D 00000 S A S A S A S A S A S A 00 000 A S A D A S A S A S A 00000 00 000 S A S A S A 00000 A Appendix A PowerPC Instruction Set Listings B OEI 0111101011 Rc 00000 0111110010 a 00000 1000000000 a B 1000010101 0 B 1000010110 0 B 1000010111 a B 1000011000 Rc B 1000011011 Rc 00000 1000110110 0 B 1000110111 0 00000 1...

Page 399: ...bu 100111 S A d 1hz 101000 0 A d Ihzu 101001 0 A d Iha 101010 0 A d Ihau 101011 0 A d sth 101100 S A d sthu 101101 S A d Imw 6 101110 0 A d stmw 6 1 01 1 1 1 S A d Its 110000 0 A d Ifsu 110001 0 A d Ifd 110010 0 A d Ifdu 1 1 001 1 0 A d stfs 110100 S A d stfsu 1 1 01 01 S A d stfd stfdu 110110 S A d 110111 S A d Id 1 111010 0 A ds 00 Idu 1 111010 0 A ds 01 Iwa 1 1 1 1 01 0 0 A ds 1 0 fdivsx fsubsx...

Page 400: ... 1 0 0 Rc faddx 1 1 1 1 1 1 0 A 8 0 00 00 1 0 1 0 1 Rc fsqrtx 4 7 1 1 1 1 1 1 0 100000 8 O O 10 1 01 1 0 Rc r _r r_ _ _r fselx 4 1 1 1 1 1 1 0 A 8 C 1 0 1 1 1 Rc fmulx 1 1 1 1 1 1 0 A 00 000 C 1 1 0 0 1 Rc frsqrtex 4 1 1 1 1 1 1 0 0 00 0 0 8 000QOO 1 1 0 1 0 Rc r r fmsubx 1 1 1 1 1 1 0 A 8 C 1 1 1 0 0 Rc fmaddx 111111 o A 8 C 1 1 1 0 1 Rc fnmsubx 111111 o A 8 C 1 1 1 1 0 Rc fnmaddx 111111 o A 8 C ...

Page 401: ... 1100101110 fctidzx 1 111111 1100101111 fcfidx 1 111111 1101001110 A 16 Notes 1 64 bit instruction 2 Supervisor level instruction 3 Optional 64 bit bridge instruction 4 Optional instruction 5 Supervisor and user level instruction 6 load store string multiple instruction 7 32 bit instruction not implemented by the MPC750 MPC750 RISC Microprocessor User s Manual ...

Page 402: ...e 13 0 A SIMM addis 15 0 A SIMM addmex 31 0 A 234 IRe addzex 31 0 A 202 IRe divdx 1 31 0 A B PE 489 IRe divdux1 31 0 A B pE 457 IRe divwx 31 0 A B pE 491 IRe divwux 31 0 A B bE 459 IRe mulhdx1 31 0 A B 73 IRe mulhdux1 31 0 A B 9 IRe mulhwx 31 0 A B 75 IRe mulhwux 31 0 A B 11 IRe mulld 1 31 0 A B E 233 IRe mulli 07 0 A SIMM mullwx 31 0 A B bE 235 IRe negx 31 0 A I t 104 IRe subfx 31 0 A B OE 40 IRe...

Page 403: ... 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andx 31 S A B 28 31 S A B 60 28 S A UIMM 29 S A UIMM 31 S A 58 31 S A 26 31 S A 284 extsbx 31 S A 954 extshx 31 S A 922 extswx 1 31 S A 986 nandx 31 S A B 476 norx 31 S A B 124 orx 31 S A B 444 orcx 31 S A B 412 ori 24 S A UIMM oris 25 S A UIMM xorx 31 S A B 316 xori 26 S A UIMM xoris 27 S A UIMM Note 164 bit instruction A 18...

Page 404: ...te 64 bit instruction Table A 7 lnteger Shift Instructions mb 8 Rc me 9 Rc mb 2 sh Rc mb 0 sh Rc me 1 sh Rc mb 3 sh Rc MB ME Rc MB ME Rc MB ME Rc Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sldx slwx sradx sradix srawx srawix srdx srwx 31 S A 31 S A 31 S A 31 S A 31 S A 31 S A 31 S A 31 S A Note 64 bit instruction Appendix A PowerPC Instruction Set Listings B...

Page 405: ...l instruction 2 32 bit instruction not implemented by the MPC750 Table A g Floating Point Multiply Add Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fmaddx 63 D A B C 29 Rc fmaddsx 59 0 A B C 29 Rc fmsubx 63 0 A B C 28 Rc fmsubsx 59 0 A B C 28 Rc fnmaddx 63 0 A B C 31 Rc fnmaddsx 59 0 A B C 31 Rc fnmsubx 63 0 A B C 30 Rc fnmsubsx 59 0 A B C 30 Rc A...

Page 406: ...it instruction Table A 11 Floating Point Compare Instructions Name 0 5 6 7 8 9 1011 12131415161718192021 22232425262728293031 ffccmmPpou l 63 1 Crl D I O I A B 3 2 rl r I 63 CrlD b A B O _ w _ Table A 12 Floating Point Status and Control Register Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mcrfs 63 64 mffsx 63 583 Rc mtfsbOx 63 70 Rc mtfsb1x 63 3...

Page 407: ... 0 Idu 1 58 D A ds 1 Idux 1 31 D A B 53 t g Idx 1 31 D A B 21 iq Iha 42 D A d Ihau 43 D A d Ihaux 31 D A B 375 lij Ihax 31 D A B 343 I 1hz 40 D A d Ihzu 41 D A d Ihzux 31 D A B 311 Ihzx 31 D A B 279 In Iwa 1 58 D A ds 2 Iwaux 1 31 D A B 373 16 Iwax 1 31 D A B 341 t qi Iwz 32 D A d Iwzu 33 D A d Iwzux 31 D A B 55 Iwzx 31 D A B 23 I Note 1 64 bit instruction A 22 MPC750 RISC Microprocessor User s Ma...

Page 408: ...A B 215 A ds A ds A B 181 A B 149 A d A d A B 439 A B 407 A d A d A B 183 A B 151 Table A 15 lnteger Load and Store with Byte Reverse Instructions tJ 0 1 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22232425 26 27 28 29 30 31 Ihbrx Iwbrx sthbrx stwbrx 31 D A B 790 31 D A B 534 31 S A B 918 31 S A B 662 Table A 16 lnteger Load and Store Multiple Instructions Name 0 5 6 7 8 9 10 11 12 13 14 ...

Page 409: ...4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eieio 31 854 isync 19 150 Idarx 1 31 D A B 84 Iwarx 31 D A B 20 stdcx 1 31 S A B 214 stwcx 31 S A B 150 sync 31 598 Note 1 64 bit instruction Table A 19 Floating Point Load Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 1718 1920 21 2223 24 25 26 27 28 29 30 31 Ifd 50 D A d Ifdu 51 D A d Ifdux 31 D A B 631 Ifdx 31 D A B 599 Ifs 48 D A d Ifsu...

Page 410: ...A B 695 1 S A B 663 1 0 1 Optional instruction Table A 21 Floating Point Move Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fabsx 63 D B 264 fmrx 63 D B 72 fnabsx 63 D B 136 fnegx 63 D B 40 Table A 22 Branch Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bx 18 LI AA LK bcx 16 BO BI BD AA LK bcctrx 19...

Page 411: ...xor 19 crbD crbA crbB 193 merf 19 crfD Table A 24 System Linkage Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 242526 2728 29 30 31 rfi 1 2 19 rfid 1 3 19 se 17 Notes 1 Supervisor level instruction 2 Optional 64 bit bridge instruction 364 bit instruction Table A 25 Trap Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 31 TO A...

Page 412: ...truction 3 Optional 64 bit bridge instruction 4 64 bit instruction spr Table A 27 Cache Management Instructions 371 144 146 178 467 Name 0 5 6 7 8 9 1011 12131415161718192021 22232425262728293031 deba 1 3 debf debi 2 debst debt debtst debz iebi 31 A B 31 A B 31 A B 31 A B 31 pip O i A B 31 A B 31 A B 31 A B Notes 1 Optional instruction 2 Supervisor level instruction 3 32 bit instruction not implem...

Page 413: ...structions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 slbia1 2 3 31 498 slbie1 2 3 31 434 tibia 1 2 4 31 370 t1bie 1 2 31 306 t1bsync1 2 31 566 Notes 1Supervisor level instruction 2Optional instruction 3 64 bit instruction 4 32 bit instruction not implemented by the MPC750 Table A 30 External Control Instructions Name 0 5 6 7 8 9 10 11 12131415161718192021 2...

Page 414: ...tion Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcxl 16 BO BI BD IAAILKI Table A 33 SC Form oop0000 0 0 00000 0 11 I0 I Specific Instruction Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sci 17 It ooo o iil 1 000 I 000000000000000 11101 ______ __ L __ __ __ ______________________L Table A 34 D Form opeD D A d opeD D A SIM...

Page 415: ...A SIMM cmpli 10 crID L A UIMM Ibz 34 D A d Ibzu 35 D A d Ifd 50 D A d Ifdu 51 D A d Ifs 48 D A d Ifsu 49 D A d Iha 42 D A d Ihau 43 D A d 1hz 40 D A d Ihzu 41 D A d Imw 1 46 D A d Iwz 32 D A d Iwzu 33 D A d mUIii 7 D A SIMM ori 24 S A UIMM oris 25 S A UIMM stb 38 S A d stbu 39 S A d stfd 54 S A d stfdu 55 S A d stfs 52 S A d stfsu 53 S A d sth 44 S A d sthu 45 S A d stmw 1 47 S A d A 30 MPC750 RIS...

Page 416: ...IMM SIMM UIMM UIMM ds ds Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Id 1 Idu 1 Iwa 1 std 1 stdu 1 58 D 58 D 58 D 62 S 62 S Note 1 64 bit instruction opeD D opeD D opeD D opeD D opeD D opeD S opeD S opeD S opeD S opeD S A A A A A Table A 36 X Form A B A NB A B A B A B A NB A Appendix A PowerPC Instruction Set Listings ds 0 ds 1 ds 2 ds 0 ds 1 xo xo xo xo xo x...

Page 417: ...s Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andx 31 S A B 28 andcx 31 S A B 60 cmp 31 0 cmpl 31 32 cntlzdx 1 31 58 cntlzwx 31 26 dcba 2 6 31 758 dcbf 31 86 rill dcbi3 31 dcbst 31 470 54 dcbt 31 278 dcbtst 31 246 dcbz 31 1014 eciwx 31 310 ecowx 31 438 eieio 31 854 A 32 MPC750 RISC Microprocessor User s Manual ...

Page 418: ...px 63 12 lebi 31 982 Ibzux 31 0 A B 119 Ibzx 31 0 A B 87 Idarx 1 31 0 A B 84 Idux 1 31 0 A B 53 Idx 1 31 0 A B 21 Ifdux 31 0 A B 631 Ifdx 31 0 A B 599 Ifsux 31 0 A B 567 Ifsx 31 0 A B 535 Ihaux 31 0 A B 375 Ihax 31 0 A B 343 Ihbrx 31 0 A B 790 Ihzux 31 0 A B 311 Ihzx 31 0 A B 279 Iswi 4 31 0 A NB 597 Iswx 4 31 0 A B 533 Iwarx 31 0 A B 20 Iwaux 1 31 0 A B 373 Appendix A PowerPC Instruction Set List...

Page 419: ...mtmsrd 1 3 178 mtsr 3 5 210 mtsrd 3 5 82 mtsrin 3 5 242 mtsrdln 3 5 114 nandx 31 S A B 476 norx 31 S A B 124 orx 31 S A B 444 orcx 31 S A B 412 slbla 1 2 3 31 498 sible 1 2 3 31 434 sldx 1 31 S A B 27 slwx 31 S A B 24 sradx 1 31 S A B 794 srawx 31 S A B 792 srawlx 31 S A SH 824 srdx 1 31 S A B 539 31 S A B 536 stbux 31 S A B 247 stbx 31 S A B 215 A 34 MPC750 RISC Microprocessor User s Manual ...

Page 420: ... A B 150 1 stwux 31 S A B 183 0 stwx 31 S A B 151 0 sync 31 Oe o ob O090 598 0 r _ _r td 1 31 TO A B 68 tibia 2 3 6 31 i CI Q I r bq f Q 09 370 tlbie 2 3 31 Q O CI otioo o B 306 tlbsync 2 3 31 nlOt ji1 i QO e f f OO 566 tw xorx 31 TO A 31 S A Notes 1 64 bit instruction 2 Optional instruction 3 Supervisor level instruction 4 Load store string multiple instruction 5 Optional 64 bit bridge instructio...

Page 421: ... crbD crbA crbB crxor 19 crbD crbA crbB 19 lsync I mcrf rfi 1 2 rfid 1 3 19 19 19 Notes 1 Supervisor level instruction 2 Optional 64 bit bridge instruction 3 64 bit instruction Table A 3S XFX Form opeD D spr opeD D I CRM opeD S spr opeD D tbr Specific Instructions 528 16 257 129 289 225 33 449 417 193 150 o 50 18 XO I xo XO XO Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 ...

Page 422: ...me 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2930 31 sradix 1 I 31 S A sh 413 Note 1 64 bit instruction Table A 41 XO Form opeD D A B OE XO Rc opeD D A B P XO Rc opeD D A I O ot OE xo Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx addcx addex addmex addzex divdx 1 dlvdux 1 divwx 31 D A 31 D A 31 D A 31 D A...

Page 423: ... A 232 subfzex 31 D A 200 Note 1 64 bit instruction Table A 42 A Form opeD D opeD D opeD D opeD D Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddx 63 D A B faddsx 59 D A B fdivx 63 D A B fdivsx 59 D A B III fmaddx 63 D A B fmaddsx 59 D A B fmsubx 63 D A B fmsubsx 59 D A B fmulx 63 D A 59 D A 63 D A B 59 D A B A 38 MPC750 RISC Microproce...

Page 424: ...t implemented by the MPC750 Table A 43 M Form OPCD S A SH MB ME OPCD S A B MB ME Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1920 21 22 23 24 25 26 27 28 29 30 31 rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc Table A 44 MD Form OPCD S A sh mb XO OPCD s A sh me XO Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ...

Page 425: ...me 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 192021 2223 24 25 26 27 28 29 30 31 rldclx 11r __ 3_0_ __ S __ __ A __ __ B __ ___ m_b__ __8_ ilrRR fccl rldcrx 1 30 S A B me 9 L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L _ _ Note 1 64 bit instruction A 40 MPC750 RISC Microprocessor User s Manual ...

Page 426: ...VEA OEA Supervisor 64 Bit 64 Bit Optional Form Level Only Bridge addx J XO addcx J XO addex J XO addi J D addic J D addic J D addis J D addmex J XO addzex J XO andx J X andcx J X andi J D andis J D bx J I bcx J B bcctrx J XL bclrx J XL cmp J X cmpi J D cmpl J X cmpli J D cntlzdx J J X cntlzwx J X crand J XL crandc J XL creqv J XL crnand J XL crnor J XL Appendix A PowerPC Instruction Set Listings A...

Page 427: ...ge eror XL erore XL erxor XL deba3 V X debt X debi X debst X debt X debtst X debz X divdx XO divdux XO divwx XO divwux XO eeiwx X eeowx X eieio X eqvx X extsbx X extshx X extswx X tabsx X taddx A taddsx A tetidx X tempo X tempu X tetidx X tetidzx X tetiwx X tetiwzx X tdivx A A 42 MPC750 RISC Microprocessor User s Manual ...

Page 428: ...divsx A fmaddx A fmaddsx A fmrx X fmsubx A fmsubsx A fmulx A fmulsx A fnabsx X fnegx X fnmaddx A fnmaddsx A fnmsubx A fnmsubsx A fresx A frspx X frsqrtex A fselx A fsqrtx 3 A fsqrtsx 3 A fsubx A fsubsx A icbl X Isync XL Ibz D Ibzu D Ibzux X Ibzx X Id DS Idarx X Idu DS Idux X Appendix A PowerPC Instruction Set Listings A 43 ...

Page 429: ...J D Ifdu J D Ifdux J X Ifdx y X Ifs J D Ifsu J D Ifsux y X Ifsx J X Iha J D Ihau J D Ihaux y X Ihax J X Ihbrx J X 1hz y D Ihzu J D Ihzux J X Ihzx y X Imw 2 y D Iswi 2 J X Iswx 2 y X Iwa y J DS Iwarx J X Iwaux y y X Iwax y J X Iwbrx y X Iwz J D Iwzu y D Iwzux y X Iwzx y X merf J XL merfs y X A 44 MPC750 RISC Microprocessor User s Manual ...

Page 430: ...rin 4 J J J J X mftb J XFX mtcrf J XFX mtfsbOx J X mtfsb1x J X mtfstx J XFL mtfstix J X mtmsr 4 J J J j X mtmsrd J J J X mtspr 1 J J J XFX mtsr 4 J J J J X mtsrd 4 J J J J J X mtsrdin 4 J J J J j X mtsrin 4 J j j j X mulhdx j J XO mulhdux j J XO mulhwx j XO mulhwux j XO mulldx j j XO mUIii j D mullwx J XO nandx J X negx J XO norx J X orx j X orcx j X Appendix A PowerPC Instruction Set Listings A 4...

Page 431: ...x j j MOS rldcrx j j MOS rldicx j j MO rldiclx j j MO rldicrx j j MO rldlmix j j MO rlwimix j M rlwinmx j M rlwnmx j M sc j j SC slbia j j j j X sible j j j j X sldx j j X slwx j X sradx j j X sradix j j XS srawx j X srawix j X srdx j j X srwx j X stb j 0 stbu j 0 stbux j X stbx j X std j j OS stdcx j j X stdu j j OS stdux j j X A 46 MPC750 RiSe Microprocessor User s Manual ...

Page 432: ...tfdu I D stfdux I X stfdx I X stfiwx I X stfs D stfsu I D stfsux X stfsx I X sth I D sthbrx X sthu D sthux I X sthx I X stmw 2 I D stswi 2 I X stswx 2 I X stw I D stwbrx I X stwcx I X stwu D stwux I X stwx I X subfx I XO subfcx XO subfex I XO subfic I D subfmex I XO subfzex I XO sync I X td I X Appendix A PowerPC Instruction Set Listings A 47 ...

Page 433: ...ridge tdi D tlbiaXl X tlbiex X tlbsync X tw X twi D xorx X xori D xoris D Notes 1 Supervisor and user level instruction 2 Load store string or multiple instruction 3 32 bit instruction not implemented by the MPC750 4 Instruction is optional for 64 bit implementations only A 48 MPC750 RISC Microprocessor User s Manual ...

Page 434: ...PC750 Processor Mnemonic Instruction dcba Data Cache Block Allocate fsqrt Floating Square Root Double Precision fsqrts Floating Square Root Single tibia TLB Invalidate All Table B 2 provides a list of 64 bit instructions that are not implemented by the MPC750 Table B 2 64 Bit Instructions Not Implemented by the MPC750 Processor Mnemonic Instruction cntlzd Count Leading Zeros Double Word divd Divid...

Page 435: ...n Clear Left rider Rotate Left Double Word then Clear Right rldic Rotate Left Double Word Immediate then Clear rldicl Rotate Left Double Word Immediate then Clear Left rldicr Rotate Left Double Word Immediate then Clear Right rldimi Rotate Left Double Word Immediate then Mask Insert slbia SLB Invalidate All slbie SLB Invalidate Entry sid Shift Left Double Word srad Shift Right Algebraic Double Wor...

Page 436: ... that attempts to be part of a read write operation to the same address uninterrupted by any other access to that address the term refers to the fact that the transactions are indivisible The PowerPC architecture implements atomic accesses through the Iwarxlstwcx instruction pair B BAT block address translation mechanism A software controlled array that stores the available block address translati...

Page 437: ...nch prediction The process of guessing whether a branch will be taken Such predictions can be correct or incorrect the term predicted as it is used here does not imply that the prediction is correct successful The PowerPC architecture defines a means for static branch prediction as part of the instruction encoding Branch resolution The determination of whether a branch is taken or not taken A bran...

Page 438: ...ain memory Cast outs Cache blocks that must be written to memory when a cache miss causes a cache block to be replaced Changed bit One of two page history bits found in each page table entry PTE The processor sets the changed bit if any store is performed into the page See also Page access history bits and Referenced bit Clear To cause a bit or bit field to register a value of zero See also Set Co...

Page 439: ...ion handler is identified by an exception vector offset defined by the architecture and a prefix selected via the MSR Exclusive state MEl state E in which only one caching device contains data that is also in system memory Execution synchronization A mechanism by which all instructions in execution are architecturally complete before beginning execution appearing to begin execution of the next ins...

Page 440: ...eger data manipulation instructions Integer load instructions move data from memory to GPRs and store instructions move data from GPRs to memory Guarded The guarded attribute pertains to out of order execution When a page is designated as guarded instructions and data cannot be accessed out of order H Harvard architecture An architectural model featuring separate caches for instruction and data Ha...

Page 441: ...formed it is known to be required by the sequential execution model See Out of order Instruction latency The total number of clock cycles necessary to execute an instruction and make ready the results of that instruction Interrupt An asynchronous exception On PowerPC processors interrupts are a special case of exceptions See also asynchronous exception Invalid state State of a cache entry that doe...

Page 442: ...ate view ofmemory is provided to all devices that share system memory Memory consistency Refers to agreement oflevels of memory with respect to a single processor and system memory for example on chip cache secondary cache and system memory Memory management unit MMU The functional unit that is capable of translating an effective logical address to a physical address providing protection mechanism...

Page 443: ...ial model for example speculative operations An operation is said to be perfonned out of order if at the time that it is perfonned it is not known to be required by the sequential execution model See In order Out of order execution A technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream Overflow An condition that occurs...

Page 444: ...s into smaller distinct stages or tenures respectively so that a subsequent operation can begin before the previous one has completed Precise exceptions A category of exception for which the pipeline can be stopped so instructions that preceded the faulting instruction can complete and subsequent instructions can be flushed and redispatched after exception handling has completed See Imprecise exce...

Page 445: ...h the MSR registers IR and or DR bits Record bit Bit 31 or the Rc bit in the instruction encoding When it is set updates the condition register CR to reflect the result of the operation Referenced bit One of two page history bits found in each page table entry PTE The processor sets the referenced bit whenever the page is accessed for a read or write See also Page access history bits Register indi...

Page 446: ...e Set associative Set associative Aspect of cache organization in which the cache space is divided into sections called sets The cache controller associates a particular main memory address with the contents of a particular set or region within the cache Signaling NaN A type of NaN that generates an invalid operation program exception when it is specified as arithmetic operands See Quiet NaN Signi...

Page 447: ...on synchronization Synchronous exception An exception that is generated by the execution of a particular instruction or instruction sequence There are two types of synchronous exceptions precise and imprecise System memory The physical memory available to a processor T Tenure A tenure consists of three phases arbitration transfer termination Glossary 12 There can be separate address bus tenures an...

Page 448: ...as problem state V VEA virtual environment architecture The level of the architecture that describes the memory model for an environment in which multiple devices can access memory defines aspects of the cache model defines cache control instructions and defines the time base facility from a user level perspective Implementations that conform to the PowerPC VEA also adhere to the VISA but may not ...

Page 449: ...Glossary 14 MPC750 RISC Microprocessor User s Manual ...

Page 450: ...5 12 definition 1 12 Index INDEX registers description 2 5 initialization 5 21 selection of block address translation 5 9 Boundedly undefined definition 2 33 BR bus request signal 7 4 8 8 Branch fall through 6 18 Branch folding 6 18 Branch instructions address calculation 2 53 condition register logical 2 54 A 26 description A 25 list of instructions 2 54 A 25 system linkage 2 55 2 65 A 26 trap 2 ...

Page 451: ...SYSCLK 7 29 Compare instructions floating point A 21 integer A 18 Completion completion unit resource requirements 6 30 considerations 6 16 definition 6 1 Context synchronization 2 36 Conventions xxxiii xxxvii 6 1 COP scan interface 8 37 Copy back mode 6 27 CR condition register CR logical instructions 2 54 A 26 CR description 2 3 CTR register 2 4 o DABR data address breakpoint register 2 7 DAR da...

Page 452: ... 24 Execution synchronization 2 36 Execution unit timing examples 6 18 Execution units 1 10 External control instructions 2 64 8 17 A 28 Index INDEX F Features list 1 4 Finish cycle definition 6 2 Floating point model FEOIFE1 bits 4 10 FP arithmetic instructions 2 42 A 20 FP assist exceptions 4 20 FP compare instructions 2 43 A 21 FP load instructions A 24 FP move instructions A 25 FP multiply add...

Page 453: ...eger instructions 6 33 isync 4 12 latency summary 6 31 Index 4 INDEX load and store address generation floating point 2 51 integer 2 46 byte reverse instructions 2 49 A 23 floating point load A 24 floating point move 2 44 A 25 floating point store 2 51 handling misalignment 2 45 integer load 2 46 A 22 integer multiple 2 49 integer store 2 47 A 23 memory synchronization 2 59 2 61 A 24 multiple inst...

Page 454: ...tate transitions 3 32 Memory accesses 8 4 Memory coherency bit M bit cache interactions 3 6 timing considerations 6 27 Memory control instructions description 2 62 2 66 segment register manipulation A 28 SLB management A 28 Index INDEX Memory management unit address translation flow 5 12 address translation mechanisms 5 9 5 12 block address translation 5 9 5 12 5 21 block diagrams 32 bit implement...

Page 455: ...nvironment architecture OEA xxviii 1 21 user instruction set architecture UISA xxviii 1 21 virtual environment architecture VEA xxviii 1 21 Index 6 Priorities exception 4 4 Process switching 4 12 Processor control instructions 2 56 2 60 2 65 A 27 Program exception 4 18 Program order definition 6 2 Programmable power states doze mode 10 3 full power mode with DPM enabled disabled 10 2 nap mode 10 3...

Page 456: ...escription 2 5 SR manipulation instructions 2 67 A 28 Index INDEX Segmented memory model see Memory management unit Serializing instructions 6 17 Shift rotate instructions 2 40 A 19 SIA sampled instruction address register 2 20 4 21 11 10 Signals AACK 7 14 ABB 7 5 8 8 address arbitration 7 4 8 8 address transfer 8 12 address transfer attribute 8 13 An 7 7 APn 7 7 ARTR 7 14 8 22 BG 7 4 8 8 BR 7 4 8...

Page 457: ...sters 2 4 2 6 TBST transfer burst signal 7 12 8 14 8 21 Index S TEA transfer error acknowledge signal 7 20 8 26 Termination 8 17 8 22 Thermal assist unit TAU 10 6 Thermal management interrupt exception 4 24 THRMn thermal management registers 2 21 10 7 Throughput definition 6 3 Timing considerations 6 7 Timing diagrams interface address transfer signals 8 12 burst transfers with data delays 8 32 L2...

Page 458: ...UISA description xxviii 1 21 registers 2 3 USIA user sampled instruction address register 2 20 11 10 Using DBWO timing 8 37 v INDEX Virtual environment architecture VEA xxviii 1 21 W WIMG bits 8 26 Write back definition 6 3 Write through mode W bit cache interactions 3 6 Write with atomic operation 3 26 Write with flush operation 3 26 Write with kill operation 3 26 WT write through signal 7 13 X X...

Page 459: ...III Index 10 MPC750 RISC Microprocessor User s Manual ...

Page 460: ...tronics 203 265 7741 Wyle Electronics 203 269 aD77 FLORIDA Altamonte Springs Future Electronics 407 665 7900 Clearwater FAI 813 530 1665 Future Electronics 813 530 1222 Deerfield Beach Arrow Schweber Electronics 305 429 a200 Wyle Electronics 305 420 0500 FI Lauderdale FAI 305 428 9494 Future Electronics 305 438 4043 HamiltOn Hallmark 954 677 3500 Newark 305 488 1151 Lake Mary Arrow Schweber Electr...

Page 461: ... 614 3 352 Dayton FAI 513 427 8090 FutUre Electronics 513 42 090 HamiitonlHalimark 513 439 8735 Newark 513 294 8880 Mayfield Heights Future Electronics 216 449 8996 Miamisburg Wyle Electronics 937 438 9953 Solon Arrow Schweber Electronics 216 2 990 Hamilton Hallmark 216 498 1100 Wyle Electronics 216 248 9996 Worthington HamiltOn Hallmark 614 88 313 OKLAHOMA Tulsa FAI 918 492 1500 HamiltOn Hallmark...

Page 462: ...re Electronics GmbH 49 89 957 270 SEVJerrnyn GmbH 49 6431 5080 Newark 49 2154 70011 Sasco Semiconductor 49 89 46110 SpoerleElectronic 49 6103 30 GREECE EBV Elektronik 30 13414300 HONG KONG AVNETWKKComponenlBUd 852 2357 88 Nanshing CIr lCham CO Ud 852 2333 5121 INDIA Canyon Products Ltd 91 80 558 7758 INDONESIA P T Ometraco 62 21 61 166 IRELAND Arrow 353 14595540 Future Electronics 353 6541330 Macr...

Page 463: ...o Paulo 55 11 815 4200 CHINA Beijing 66 1Q 66437222 Guangzhou 86 20 87537888 Shanghai 66 21 63747666 lianjin 66 22 25325072 DENMARK Copenhagen 45 43466393 FINLAND Helsinki 356 9 6824 400 Direct Sales Lines 358 9 6624 4044 358 9 6824 4045 FRANCE Paris 33134 635900 GERMANY LangenhageniHanover 49 511 786880 Munich 498992103 0 Nuremberg 49 91196 3190 Sindelfingen 49 7031 79710 Wiesbaden 49611 973050 H...

Page 464: ...ion Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation L2 Cache Interface Operation Power and Thermal Management Performance Monitor PowerPC Instruction Set Listings Instructions Not Implemented g Glossary of Terms and Abbreviations Index ...

Page 465: ...on Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation L2 Cache Interface Operation Power and Thermal Management Performance Monitor PowerPC Instruction Set Listings II Instructions Not Implemented Glossary of Terms and Abbreviations Index ...

Page 466: ...Manual exists in two versions See the Preface for a description of the following two versions PowerPC Microprocessor Family The Programming Environments Rev 1 Order MPCFPEIAD PowerPC Microprocessor Family The Programming Environments for 32 Bit Microprocessors Rev 1 Order MPCFPE32B AD Call the Motorola LDC at 1 800 441 2447 website http ldc nmd com or contact your local sales office to obtain copi...

Page 467: ......

Page 468: ......

Search results

Summary of Contents for PowerPC MPC750

Reviews:

Related manuals for PowerPC MPC750

Brands by name

Popular brands

Motorola PowerPC MPC750, User Manual

Search results

Summary of Contents for PowerPC MPC750

Reviews:

Related manuals for PowerPC MPC750

Brands by name

Popular brands