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Memory Maps

MVME197/D1

3-9

Table 3-6. VMEchip2 Memory Map

(Sheet 1 of 4)

VMEchip2 LCSR Base Address = $FFF40000

OFFSET:

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

VMEbus SLAVE ENDING ADDRESS 1

VMEbus SLAVE STARTING ADDRESS 1

VMEbus SLAVE ENDING ADDRESS 2

VMEbus SLAVE STARTING ADDRESS 2

VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 1

VMEbus SLAVE ADDRESS TRANSLATION SELECT 1

VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 2

VMEbus SLAVE ADDRESS TRANSLATION SELECT 2

(VB)
SNP

(VB)

(VB)
SUP

(VB)
USR

(VB)

A32

(VB)

A24

(VB)

D64

(VB)
BLK

(VB)

PGM

(VB)
DAT

(VB)
SNP

(VB)

(VB)
SUP

(VB)
USR

(VB)

A32

(VB)

A24

(VB)

D64

(VB)
BLK

(VB)

PGM

(VB)
DAT

LOCAL BUS SLAVE ENDING ADDRESS 1

LOCAL BUS SLAVE STARTING ADDRESS 1

LOCAL BUS SLAVE ENDING ADDRESS 2

LOCAL BUS SLAVE STARTING ADDRESS 2

LOCAL BUS SLAVE ENDING ADDRESS 3

LOCAL BUS SLAVE STARTING ADDRESS 3

LOCAL BUS SLAVE ENDING ADDRESS 4

LOCAL BUS SLAVE STARTING ADDRESS 4

LOCAL BUS SLAVE ADDRESS TRANSLATION ADDRESS 4

LOCAL BUS SLAVE ADDRESS TRANSLATION SELECT 4

(LB)
D16

(LB)

(LB) AM 4

(LB)
D16

(LB)

(LB) AM 3

(LB)
D16

(LB)

(LB) AM 2

(LB)
D16

(LB)

(LB) AM 1

(VB) GCSR GROUP ADDRESS

(VB) GCSR

BOARD

ADDRESS

EN4

EN3

EN2

EN1

D16

ROM
SIZE

(XX)

ROM BANK B

SPEED

(XX)

ROM BANK A

SPEED

(XX)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

= Local Bus

(LB) = Local Bus Slave

= Local Bus to VMEbus

= VMEbus

(VB) = VMEbus Slave

(XX) = Not Used on the MVME197 Series

Summary of Contents for MVME197DP

Page 1: ...MVME197DP and MVME197SP Single Board Computers User s Manual MVME197 D1 ...

Page 2: ...r written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Rights L...

Page 3: ...a character which specifies the numeric format as follows For example 12 is the decimal number twelve and 12 is the decimal number eighteen Unless otherwise specified all address references are in hexadecimal throughout this document An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following th...

Page 4: ... as shown below Any attempt to use small endian byte ordering will immediately render the MVME197Bug debugger unusable The terms control bit and status bit are used extensively in this document The term control bit is used to describe a bit in a register that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it cont...

Page 5: ...nt bears the same number as the manual but has a suffix such as A1 the first supplement to the manual Document Title Motorola Publication Number MVME197LE MVME197DP and MVME197SP Single Board Computers Programmer s Reference Guide MVME197BUG 197Bug Debugging Package User s Manual MVME197BUG 197Bug Diagnostic Firmware User s Guide MVME197DP and MVME197SP Single Board Computer Support Information MV...

Page 6: ...ser s Manual SGS Thompson MK48T08 NVRAM TOD Clock Data Sheet The following non Motorola publications may also be of interest and may be obtained from the sources indicated The VMEbus Specification is contained in ANSI IEEE Standard 1014 1987 ANSI IEEE Std 1014 1987 The Institute of Electrical and Electronics Versatile Backplane Bus VMEbus Engineers Incorporated Publication and Sales Department 345...

Page 7: ...arks of their respective holders Copyright Motorola 1994 All Rights Reserved Printed in the United States of America March 1994 WARNING This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the documentation for this product may cause interference to radio communications It has been tested and found to comply with the limits for a Cla...

Page 8: ... not remove equipment covers Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power ...

Page 9: ...ion Switches 2 3 Configuration Switch S1 General Information 2 3 Configuration Switch S1 General Purpose Functions S1 1 to S1 8 2 4 Configuration Switch S1 System Controller Enable Function S1 9 2 4 Configuration Switch S6 Serial Port 4 Clock Select S6 1 S6 2 2 5 Connectors 2 5 Installation Instructions 2 6 MVME197 Module Installation 2 6 System Considerations 2 7 CHAPTER 3 OPERATING INSTRUCTIONS ...

Page 10: ... Description 4 1 Data Bus Structure 4 1 MC88110 MPU 4 4 MC88410 Cache Controller 4 4 BOOT ROM 4 4 Flash Memory 4 4 Onboard DRAM 4 4 Battery Backup RAM and Clock 4 5 VMEbus Interface 4 5 I O Interfaces 4 5 Serial Port Interface 4 5 Printer Interface 4 6 Ethernet Interface 4 6 SCSI Interface 4 7 SCSI Termination 4 7 Peripheral Resources 4 8 Programmable Tick Timers 4 8 Watchdog Timer 4 8 Software Pr...

Page 11: ...SP Switches Connectors and LED Indicators Location Diagram 2 2 Figure 4 1 MVME197SP Block Diagram 4 2 Figure 4 2 MVME197DP Block Diagram 4 3 Figure A 1 Middle of the Road EIA 232 D Configuration A 5 Figure A 2 Minimum EIA 232 D Connection A 6 ...

Page 12: ...xii ...

Page 13: ...gister Memory Map 3 8 Table 3 6 VMEchip2 Memory Map 3 9 Table 3 7 PCCchip2 Memory Map 3 13 Table 3 8 Printer Memory Map 3 14 Table 3 9 Cirrus Logic CD2401 Serial Port Memory Map 3 15 Table 3 10 82596CA Ethernet LAN Memory Map 3 16 Table 3 11 53C710 SCSI Memory Map 3 17 Table 3 12 MK48T08 BBRAM TOD Clock Memory Map 3 17 Table 3 13 BBRAM Configuration Area Memory Map 3 18 Table 3 14 TOD Clock Memory...

Page 14: ...xiv ...

Page 15: ... clock with battery backup an Ethernet transceiver interface four serial ports with EIA 232 D interface six tick timers a watchdog timer 256KB of BOOT ROM a SCSI bus interface with DMA Direct Memory Access a Centronics printer port an A16 A24 A32 D8 D16 D32 VMEbus master slave interface and a VMEbus system controller Input Output I O signals are routed through the MVME197 s backplane connector P2 ...

Page 16: ...uch devices are required on the MVME197 to accommodate the 64 bit data bus of the MC88110 microprocessor Single bit error correction and double bit detection is performed in the ECDM The PCCchip2 Peripheral Channel Controller ASIC provides two tick timers and the interface to the LAN chip the SCSI chip the serial port chip the printer port and the BBRAM Battery Backup RAM The VMEchip2 ASIC provide...

Page 17: ...obytes of BOOT ROM Six 32 bit tick timers for periodic interrupts Watchdog timer Eight software interrupts I O SCSI Bus interface with Direct Memory Access DMA Four serial ports with EIA 232 D buffers Centronics printer port Ethernet transceiver interface VMEbus interface VMEbus system controller functions VMEbus interface to local peripheral bus A24 A32 D8 D16 D32 BLT D8 D16 D32 D64 BLT Block Tra...

Page 18: ...PC board Height Width Thickness PC board with connectors and front panel Height Width Thickness Board connectors P1 connector P2 connector J1 connector J4 connector 5 Vdc 2 5 4 8 A typical 5 8 A maximum 12 Vdc 2 5 100 mA maximum 12 Vdc 2 5 100 mA maximum 0 to 55 C at point of entry of forced air approximately 490 LFM 40 to 85 C 5 to 90 non condensing Double high VMEboard 9 187 inches 233 35 mm 6 2...

Page 19: ...nditions it may be possible to operate the module reliably at higher than 55 C with increased airflow It is important to note that there are several factors in addition to the rated CFM of the air mover which determine the actual volume and speed of air flowing over a module FCC Compliance The MVME197 was tested in an FCC compliant chassis and meets the requirements for Class A equipment FCC compl...

Page 20: ...pheral devices They connect the MVME197 to EIA 232 D serial devices Centronics compatible parallel devices SCSI devices and Ethernet devices A P2 Adapter Board or LCP2 Adapter Board and cable is required with the MVME712 series transition modules Refer to the MVME712 12 MVME712 13 MVME712A MVME712AM and MVME712B Transition Modules and LCP2 Adapter Board User s Manual or the MVME712M Transition Mod...

Page 21: ...ing materials for storing or reshipping of the equipment Caution Avoid touching areas of integrated circuits Static discharge can damage these components Inspect the equipment for any shipping damage If no damage exists then the module can be prepared for operation according to the following sections of this chapter Hardware Preparation To select the desired configuration and ensure proper operati...

Page 22: ...OR P1 FAIL LAN RUN A1 B1 C1 A1 B1 C1 DS6 DS5 SCON DS3 VME SCSI ABORT SWITCH S2 RESET SWITCH S3 1E1 1A17 1E17 1A1 1E1 2A17 2E17 3A1 3E1 3A17 3E17 VMEbus CONNECTOR P2 CONFIGURATION SWITCH S6 SERIAL PORT 4 CLOCK SELECT S6 MEZZANINE CONNECTOR J1 MVME197 O N 1 2 S1 O N 1 2 3 4 5 6 7 8 9 J4 1 10 Figure 2 1 MVME197DP SP Switches Connectors and LED Indicators Location Diagram ...

Page 23: ...figuration Switch S1 General Information Switch S1 is a bank of nine two way switch segments The following illustration shows the factory configuration of switch S1 The bit values are read as a one when the switch is OFF open and as a zero when the switch is ON closed The default value for switch S1 is shown below Switch S1 System Controller SCON General Purpose Input 7 GPI7 General Purpose Input ...

Page 24: ...put lines disabled open Configuration Switch S1 System Controller Enable Function S1 9 The MVME197DP SP can be the system controller The system controller function is enabled or disabled by configuring selectable switch segment S1 9 When the MVME197DP SP is the system controller the SCON LED is turned ON The VMEchip2 may be configured as a system controller as illustrated below Factory configurati...

Page 25: ...The MVME197DP SP has two 64 position DIN connectors P1 and P2 Connector P1 rows A B C and connector P2 row B provide the VMEbus interconnection Connector P2 rows A and C provide the interconnect to the SCSI bus the serial ports the Ethernet interface and the Centronics printer The 249 pin mezzanine connector J1 refer to the note below provides the MVME197DP SP modules series with an MC88110 bus in...

Page 26: ... considerations Ensure that the BOOT ROM device is installed Ensure that all switches are configured as desired MVME197 Module Installation Now that the MVME197DP or MVME197SP module is ready for installation proceed as follows a Turn all equipment power OFF and disconnect the power cable from the power source Caution Inserting or removing modules while power is applied could result in damage to m...

Page 27: ... the manuals listed in Related Documentation section for information on installing the P2 Adapter Board and the MVME712X transition module Some connection diagrams are provided in the MVME197LE MVME197DP and MVME197SP Single Board Computers Programmer s Reference Guide Some cable s are not provided with the MVME712X module and therefore are made or provided by the user Motorola recommends using sh...

Page 28: ... the system to hang up There is only one situation in which the system might lack this global bus timeout when the MVME197 is not the system controller and there is no global bus timeout elsewhere in the system Multiple MVME197 modules may be configured into a single VME card cage In general hardware multiprocessor features are supported Other MPUs on the VMEbus can interrupt disable communicate w...

Page 29: ...Computers Programmer s Reference Guide for more information RESET Switch S3 The RESET switch S3 will reset all the onboard devices and drive the SYSRESET signal if the MVME197 module is the system controller The RESET switch S3 will reset all the onboard devices with the exception of the DCAM and ECDM if the MVME197 module is not the system controller The VMEchip2 generates the SYSRESET signal The...

Page 30: ...al line is active 2 The green SCON LED DS2 is lit when the VMEchip2 is the VMEbus system controller 3 The green RUN LED DS3 is lit when the MC88110 bus MC pin is low 4 The green LAN LED DS4 lights when the LAN chip is the local peripheral bus master 5 The green VME LED DS5 lights when the board is using the VMEbus or when the board is accessed by the VMEbus 6 The green SCSI LED DS6 lights when the...

Page 31: ...rface The Processor Bus to Local Peripheral Bus and the Local Peripheral Bus to Processor Bus decoders are programmed in the BusSwitch The Local Peripheral to VMEbus master and VMEbus to Local Peripheral Bus slave decoders are programmed in the VMEchip2 2 Size is approximate 3 Cache inhibit depends on devices in area mapped 4 This area is not decoded If these locations are accessed and the local p...

Page 32: ...F reserved 4KB 4 FFF06000 FFF06FFF reserved 4KB 4 FFF07000 FFF07FFF User defined 4KB 4 FFF08000 FFF3FFFF reserved 224KB 4 FFF40000 FFF400FF VMEchip2 LCSR D32 256B 1 2 3 FFF40100 FFF401FF VMEchip2 GCSR D32 D8 256B 1 2 3 FFF40200 FFF40FFF reserved 3 5KB 4 5 FFF41000 FFF41FFF reserved 4KB 4 FFF42000 FFF42FFF PCCchip2 D32 D8 4KB 1 2 FFF43000 FFF43FFF reserved 4KB 4 FFF44000 FFF44FFF reserved 4KB 3 FFF...

Page 33: ...EA signal 5 Size is approximate 6 Port commands to the 82596CA must be written as two 16 bit writes upper word first and lower word second 7 DROM BOOT ROM appears at 0 following a local peripheral bus reset The DROM appears at 0 until the DR0 bit is cleared in the PCCchip2 In addition the ROM0 bit in the ROMCR register of the BusSwitch must be cleared before the DRAM is accessed Detailed I O Memor...

Page 34: ...SSAR1 SEAR1 SSAR2 SEAR2 30 SSAR3 SEAR3 SSAR4 SEAR4 38 STR1 STSR1 STR2 STSR2 40 STR3 STSR3 STR4 STSR4 48 PAR1 PAR2 PAR3 PAR4 SAR1 SAR2 SAR3 SAR4 50 BTIMER PADJUST PCOUNT PAL 58 WPPA WPTPA WPPAT 60 ROMCR TCTRL1 TCTRL2 LEVEL MASK ISEL0 ISEL1 68 ABORT CPINT TINT1 TINT2 WPINT PALINT XINT VBASE 70 TCOMP1 TCOUNT1 78 TCOMP2 TCOUNT2 80 GPR1 GPR2 88 GPR3 GPR4 90 XCTAGS 100 XCCR VECTOR1 108 VECTOR2 VECTOR3 1...

Page 35: ...N1 03 ECDMID1 04 MEMCON2 05 ECDMID2 06 MEMCON3 07 ECDMID3 08 SYNSTAT0 09 ERSTAT0 0A SYNSTAT1 0B ERSTAT1 0C SYNSTAT2 0D ERSTAT2 0E SYNSTAT3 0F ERSTAT3 10 I2CON0 11 I2STAT0 12 I2CON1 13 I2STAT1 14 I2CON2 15 I2STAT2 16 I2CON3 17 I2STAT3 18 I2DATA0 19 I2ADDR0 1A I2DATA1 1B I2ADDR1 1C I2DATA2 1D I2ADDR2 1E I2DATA3 1F I2ADDR3 D63 D56 D55 D48 D47 D40 D39 D32 D31 D24 D23 D16 D15 D8 D7 D0 ECDM register map...

Page 36: ...RMWRMOE6 RMWRMOE5 RMWRMOE4 RMWRMOE3 RMWRMOE2 RMWRMOE1 RMWOE5 0F 15 CSRTAIL7 CSRTAIL6 CSRTAIL5 CSRTAIL4 CSRTAIL3 CSRTAIL2 CSRTAIL1 NOT USED 10 16 BWRTTL4 BWRTTL3 BWRTTL2 BWRTTL1 RMWOE4 RMWOE3 RMWOE2 RMWOE1 11 17 SECCLKSL RMWOCKSL BWRITE5 BWRITE4 BWRITE3 BWRITE2 BWRITE1 WRCLKSEL 12 18 NOT USED NOT USED RMW5 RMW4 RMW3 RMW2 RMW1 NOT USED 13 19 RMWTAIL7 RMWTAIL6 RMWTAIL5 RMWTAIL4 RMWTAIL3 RMWTAIL2 RMWT...

Page 37: ...14 LOCAL BUS SLAVE ENDING ADDRESS 1 LOCAL BUS SLAVE STARTING ADDRESS 1 18 LOCAL BUS SLAVE ENDING ADDRESS 2 LOCAL BUS SLAVE STARTING ADDRESS 2 1C LOCAL BUS SLAVE ENDING ADDRESS 3 LOCAL BUS SLAVE STARTING ADDRESS 3 20 LOCAL BUS SLAVE ENDING ADDRESS 4 LOCAL BUS SLAVE STARTING ADDRESS 4 24 LOCAL BUS SLAVE ADDRESS TRANSLATION ADDRESS 4 LOCAL BUS SLAVE ADDRESS TRANSLATION SELECT 4 28 LB D16 EN LB WP EN ...

Page 38: ...T VMEbus INTERRUPT LEVEL VMEbus INTERRUPT VECTOR DMAC INTERRUPT COUNTER MPU CLR MPU LB EN MPU LB PERR MPU LB OB MPU LB TO DMAC LB EN DMAC LB PERR DMAC LB OB DMAC LB TO DMAC LB ERR DMAC VME ERR DMAC DONE 4C VB TO DMAC TIME OFF DMAC TIME ON VMEbus GLOBAL TIMEOUT VMEbus ACCESS TIMEOUT LOCAL BUS TIMEOUT WATCHDOG TIMEOUT PRESCALER ADJUST 50 TICK TIMER 1 COMPARE 54 TICK TIMER 1 COUNTER 58 TICK TIMER 2 C...

Page 39: ...7 CLR IRQ 26 CLR IRQ 25 CLR IRQ 24 CLR IRQ 23 CLR IRQ 22 CLR IRQ 21 CLR IRQ 20 CLR IRQ 19 CLR IRQ 18 CLR IRQ 17 CLR IRQ 16 CLR IRQ 15 CLR IRQ 14 CLR IRQ 13 CLR IRQ 12 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 78 ACFAIL IRQ LEVEL ABORT IRQ LEVEL SYSFAIL IRQ LEVEL MASTER WRITE POST ERROR IRQ LEVEL PARITY ERROR IRQ LEVEL IRQ1 EDGE SENSITIVE IRQ LEVEL TICK TIMER 2 IRQ LEVEL TICK TIMER 1 IRQ LEVEL 7C V...

Page 40: ... PURPOSE CONTROL AND STATUS REGISTER 0 C 6 GENERAL PURPOSE CONTROL AND STATUS REGISTER 1 10 8 GENERAL PURPOSE CONTROL AND STATUS REGISTER 2 14 A GENERAL PURPOSE CONTROL AND STATUS REGISTER 3 18 C GENERAL PURPOSE CONTROL AND STATUS REGISTER 4 1C E GENERAL PURPOSE CONTROL AND STATUS REGISTER 5 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTES L Local Bus Offset V VMEbus Offset Table 3 6 VM...

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