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Motorola MVME177 Installation And Use Manual Download Page 48

Operating Instructions

3-6

3

2

.

This area is user-programmable. The suggested use is shown in

the table. The DRAM decoder is programmed in the MCECC chip,
and the local-to-VMEbus decoders are programmed in the
VMEchip2.

3. Size is approximate.

4

.

Cache inhibit depends on devices in area mapped.

5. This area is not decoded. If these locations are accessed and the
local bus timer is enabled, the cycle times out and is terminated by
a TEA signal.

6. The SRAM has optional battery backup on the MVME177.

The following table focuses on the Local I/O Devices portion of the
local bus Main Memory Map.

Table 3-2. Local I/O Devices Memory Map

Address Range

Devices Accessed

Port Size

Size

Notes

$FFF00000 - $FFF3FFFF

Reserved

--

256KB

5

$FFF40000 - $FFF400FF

VMEchip2 (LCSR)

D32

256B

1,4

$FFF40100 - $FFF401FF

VMEchip2 (GCSR)

D32-D8

256B

1,4

$FFF40200 - $FFF40FFF

Reserved

--

3.5KB

5,7

$FFF41000 - $FFF41FFF

Reserved

--

4KB

5

$FFF42000 - $FFF42FFF

PCCchip2

D32-D8

4KB

1

$FFF43000 - $FFF430FF

MCECC #1

D8

256B

1

$FFF43100 - $FFF431FF

MCECC #2

D8

256B

1

$FFF43200 - $FFF43FFF

MCECCs (repeated)

--

3.5KB

1,7

$FFF44000 - $FFF44FFF

Reserved

--

4KB

5

$FFF45000 - $FFF451FF

CD2401 (Serial Comm. Cont.) D16-D8

512B

1,9

$FFF45200 - $FFF45DFF Reserved

--

3KB

7,9

$FFF45E00 - $FFF45FFF Reserved

--

512B

1,9

$FFF46000 - $FFF46FFF

82596CA (LAN)

D32

4KB

1,8

$FFF47000 - $FFF47FFF

53C710 (SCSI)

D32/D8

4KB

1

$FFF48000 - $FFF4FFFF

Reserved

--

32KB

5

$FFF50000 - $FFF6FFFF

Reserved

--

128KB

5

$FFF70000 - $FFF76FFF

Reserved

--

28KB

6

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Summary of Contents for MVME177

Page 1: ...MVME177 Single Board Computer Installation and Use Manual VME177A IH2 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...els This manual is intended for anyone who wants to design OEM systems supply additional capability to an existing compatible system or work in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed To use this manual you should be familiar with the publications listed in the Related Documentation section in Chapter 1 of this manual MVME177 001 MVME...

Page 4: ...tered trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola Inc 1995 1996 All Rights Reserved Printed in the United States of America June 1996 European Notice Board products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the f...

Page 5: ...l or other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 6: ......

Page 7: ...reparation 2 4 Setup Instructions 2 10 MVME177 Module Installation Instructions 2 12 System Considerations 2 15 Introduction 3 1 Controls and Indicators 3 1 ABORT Switch S1 3 1 RESET Switch S2 3 2 Front Panel Indicators DS1 DS4 3 3 Memory Maps 3 4 Local Bus Memory Map 3 4 Normal Address Range 3 4 Software Initialization 3 8 Multi MPU Programming Considerations 3 8 Local Reset Operation 3 8 Introdu...

Page 8: ...ation 4 18 Timing Performance 4 18 Local Bus to DRAM Cycle Times 4 18 ROM Cycle Times 4 19 SCSI Transfers 4 19 LAN DMA Transfers 4 20 Remote Status and Control 4 20 Introduction A 1 Levels of Implementation A 3 Signal Adaptations A 4 Sample ConÞgurations A 4 Proper Grounding A 7 Overview of M68000 Firmware B 1 Description of 177Bug B 1 177Bug Implementation B 3 Autoboot B 3 ROMboot B 5 Network Boo...

Page 9: ...odule B 21 TFTP Protocol Module B 21 Network Boot Control Module B 22 Network I O Error Codes B 22 Multiprocessor Support B 22 Multiprocessor Control Register MPCR Method B 22 GCSR Method B 24 Diagnostic Facilities B 25 Using the 177Bug Debugger B 27 Entering Debugger Command Lines B 27 Syntactic Variables B 28 Expression as a Parameter B 29 Address as a Parameter B 31 Address Formats B 31 Offset ...

Page 10: ...uration Acceptable Entries B 48 Erase Test B 48 Flash Fill Test B 48 Flash Patterns Test B 49 Default Flash Test ConÞguration B 50 SFLASH Command B 51 The 177Bug Debugger Command Set B 53 Disk Tape Controller Modules Supported C 1 Disk Tape Controller Default ConÞgurations C 2 IOT Command Parameters for Supported Floppy Types C 5 ConÞgure Board Information Block D 1 Set Environment to Bug Operatin...

Page 11: ...List of Figures MVME177 Switches Headers Connectors Polyswitches and LEDs 2 5 MVME177 Block Diagram 4 3 ...

Page 12: ...tions 1 1 MVME177 Features 1 2 MVME177 SpeciÞcations 1 4 Start up Overview 2 2 ConÞguring MVME177 Headers 2 6 Local Bus Memory Map 3 5 Local I O Devices Memory Map 3 6 EPROM and Flash Control and ConÞguration 4 5 Diagnostic Test Groups B 26 ...

Page 13: ...peed Major Differences MVME177 001 50 MHz MC68060 4MB Onboard ECC DRAM MVME177 002 50 MHz MC68060 8MB Onboard ECC DRAM MVME177 003 50 MHz MC68060 16MB Onboard ECC DRAM MVME177 004 50 MHz MC68060 32MB Onboard ECCDRAM MVME177 005 50 MHz MC68060 64MB Onboard ECC DRAM MVME177 006 50 MHz MC68060 128MB Onboard ECC DRAM MVME177 011 60 MHz MC68060 4MB Onboard ECC DRAM MVME177 012 60 MHz MC68060 8MB Onboar...

Page 14: ...power SCSI and VME RAM 8K by 8 RAM and time of day clock with battery backup Switches RESET ABORT Tick timers Four 32 bit tick timers for periodic interrupts Watchdog timer One watchdog timer Software interrupts Eight software interrupts I O SCSI Bus interface with DMA Four serial ports with EIA 232 D buffers with DMA 8 bit bidirectional parallel port Ethernet transceiver interface with DMA VMEbus...

Page 15: ...sity system configuration An assembly of three axial fans rated at 100 CFM per fan is placed directly under the VME card cage The incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high ...

Page 16: ...ification information for the system board platform Table 1 3 MVME177 Specifications Characteristics SpeciÞcations Power requirements with both EPROM sockets populated and excluding external LAN transceiver 5 Vdc 5 4 5 A typical 6 0 A max at 50 MHz with 128MB ECC DRAM 12 Vdc 5 100 mA max 1 0 A max with offboard LAN transceiver 12 Vdc 5 100 mA max Operating temperature refer to Cooling Requirements...

Page 17: ...onnecting shields to earth ground 4 Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented failure to do so could compromise the FCC compliance of the equipment containing the module General Description The MVME177 is a double high VMEmodule based on the MC68060 microprocessor The MVME177 has 4 8 16 32 64 128 256 MB of ECC protected ...

Page 18: ...ts the following transition boards MVME712 12 MVME712 13 MVME712M MVME712A MVME712AM MVME712B referred to in this manual as MVME712x unless separately specified The MVME712x transition boards provide configuration headers and industry standard connectors for the I O devices The VMEbus interface is provided by an ASIC called the VMEchip2 The VMEchip2 includes Two tick timers A watchdog timer Progra...

Page 19: ...rs can be D8 D16 D32 VMEchip2 DMA transfers to the VMEbus however can be D16 D32 D16 BLT D32 BLT D64 MBLT The PCCchip2 ASIC provides Two tick timers Interface to the LAN chip SCSI chip Serial port chip Parallel printer port BBRAM The MCECC memory controller ASIC provides the programmable interface for the ECC protected DRAM mezzanine board ...

Page 20: ...debug monitor firmware 177Bug is provided in the two EPROMs in sockets on the MVME177 main module It provides Over 50 debug up downline load and disk bootstrap load commands Full set of onboard diagnostics One line assembler disassembler 177Bug includes a user interface which accepts commands from the system console terminal 177Bug can also operate in a System Mode which includes choices from a se...

Page 21: ...s office for more details Related Documentation The following publications are applicable to the MVME177 and may provide additional helpful information If not shipped with this product they may be purchased by contacting your local Motorola sales office Non Motorola documents may be purchased from the sources listed Note Although not shown in the following list each Motorola Computer Group manual ...

Page 22: ...ering Documents P O Box 19539 Irvine CA 92714 CL CD2400 2401 Four Channel Multi Protocol Communications Controller Data Sheet order number 542400 003 Cirrus Logic Inc 3100 West Warren Ave Fremont CA 94538 Document Title Motorola Publication Number 177Bug Diagnostics UserÕs Manual V177DIAA UM Debugging Package for Motorola 68K CISC CPUs User s Manual 68KBUG1 D and 68KBUG2 D Single Board Computers S...

Page 23: ...poration Microelectronics Products Division Colorado Springs CO MK48T08 Timekeeper TM and 8Kx8 Zeropower TM RAM data sheet in Static RAMs Databook SGS THOMPSON Microelectronics Group North South American Marketing Headquarters 1000 East Bell Road Phoenix AZ 85022 2699 DS1643 Nonvolatile Timekeeping RAM Dallas Semiconductor Data Manual 4401 South Beltwood Parkway Dallas Texas 75244 3292 Support Inf...

Page 24: ...h to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows A byte is...

Page 25: ... manuals Refer to Related Documentation in Chapter 1 Unpacking Instructions Note If the shipping carton is damaged upon receipt request carrier s agent be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment Caution Avoid touching areas of ...

Page 26: ...nect and install the transition board P2 adapter module and optional SCSI device cables The userÕs manual you received with your MVME712 module listed in Related Documentation 1 9 You may also wish to obtain the Single Board Computer SCSI Software UserÕs Manual listed in Related Documentation 1 9 Connect a console terminal to the MVME712 Installation Instructions 2 12 The userÕs manual you receive...

Page 27: ...listed in Related Documentation 1 9 Initialize the clock Installation Instructions 2 12 Debugger General Information B 1 Examine and or change environmental parameters Installation Instructions 2 12 Environment Command D 3 Program the PPCchip2 and VMEchip2 Memory Maps 3 4 You may also wish to obtain the Single Board Computers ProgrammerÕs Reference Guide listed in Related Documentation 1 9 Table 2...

Page 28: ... s Reference Guide as listed in Related Documentation in Chapter 1 The location of switches jumper headers connectors and LED indicators on the MVME177 is illustrated in Figure 2 1 The MVME177 has been factory tested and is shipped with the factory jumper settings described in the following sections The MVME177 operates with its required and factory installed Debug Monitor MVME177Bug 177Bug with t...

Page 29: ... MVME 177 PRIMARY SIDE P2 A32 B32 C32 A1 B1 C1 19 20 J3 DS1 1 2 STAT FAIL RUN SCON LAN SCSI VME ABORT RESET J2 1 12V XU2 XU1 3 J9 J10 COMPONENTS ARE REMOVED FOR CLARITY 60 59 2 1 P4 60 59 2 1 P5 MEZZANINE BOARD DS2 DS3 DS4 2 3 4 J6 3 1 J8 1 2 J7 1 2 J1 2 16 15 1 F1 F2 1 3 1 39 40 1 6 7 2 29 28 18 17 29 28 18 17 39 40 1 6 7 2 POLYSWITCH ...

Page 30: ...le jumpers GPI0 GPI2 User deÞnable GPI3 Reserved GPI4 GPI7 User deÞnable 1 2 GPI0 3 4 GPI1 5 6 GPI2 9 10 GPI4 11 12 GPI5 13 14 GPI6 15 16 GPI7 Factory conÞguration 1 2 J2 SRAM backup power source select header VMEbus 5V STBY 2 1 Factory conÞguration 3 Backup power disabled 4 2 Backup from battery 3 2 15 GPI0 GPI1 GPI2 GPI6 GPI3 GPI4 GPI5 1 2 16 GPI7 7 8 1 2 3 4 1 2 3 4 1 2 3 4 ...

Page 31: ...hermalsensing pins Connected to MC68060 internal thermal resistor None Factory conÞguration 5 J8 EPROM Flash conÞguration jumper 1MB EPROM and 2MB Flash enabled 1 2 Factory conÞguration 6 4 MB Flash enabled None Table 2 2 Configuring MVME177 Headers Continued Header Number Header Description ConÞguration Jumpers Notes 3 2 1 3 2 1 3 2 1 THERM2 THERM1 2 1 2 1 ...

Page 32: ...purpose readable jumpers on header J1 can be read as I O control register 3 at FFF40088 bits 0 7 in the VMEchip2 LCSR see Chapter 4 VMEchip2 The bit values are read as a 1 when the jumper is off and as a 0 when the jumper is on 2 On the MVME177 pins 7 and 8 bit 3 are removed for board ID and the bit value is reserved Table 2 2 Configuring MVME177 Headers Continued Header Number Header Description ...

Page 33: ...a non active backplane 5 The thermal sensing pins THERM1 and THERM2 are connected to an internal thermal resistor and provide information about the average temperature of the processor Refer to the M68000 Microprocessors UserÕs Manual for additional information on the use of these pins 6 The FLASH jumper J8 is used to select the Flash memory and EPROM conÞguration on the MVME177 If the board is co...

Page 34: ...application a Jumpers on header J1 affect 177Bug operation as listed below The default condition is with seven jumpers installed between the following pairs of pins The MVME177 may be configured with these readable jumpers These jumpers can be read as a register at FFF40088 in the VMEchip2 LCSR The bit values are read as a one when the jumper is off and as a zero when the jumper is on This jumper ...

Page 35: ...or your particular chassis or system for details concerning the installation of the MVME177 Bit J1 Pins Description Bit 0 GPI0 1 2 When this bit is a one high it instructs the debugger to use local Static RAM for its work page i e variables stack vector tables etc Bit 1 GPI1 3 4 When this bit is a one high it instructs the debugger to use the default setup operation parameters in ROM versus the us...

Page 36: ...rd slot s at the front and rear of the chassis if the chassis has a rear card cage The MVME177 module requires power from both P1 and P2 It may be installed in any double height unused card slot if it is not configured as system controller If the MVME177 is configured as system controller it must be installed in the leftmost card slot slot 1 to correctly initiate the bus grant daisy chain and to h...

Page 37: ...r s Reference Guide Some cable s are not provided with the MVME712x module s and therefore are made or provided by the user Motorola recommends using shielded cables for all connections to peripherals to minimize radiation Connect the peripherals to the cable s Detailed information on the EIA 232 D signals supported is found in Appendix A 7 Connect the terminal to be used as the 177Bug system cons...

Page 38: ... reconfigured by programming the MVME177 CD2401 Serial Controller Chip SCC or by using the 177Bug PF command Note that the MVME177 also contains a parallel port To use a parallel device such as a printer with the MVME177 connect it to the printer port at P2 through an MVME712x transition module Refer to the MVME177 Single Board Computers Programmer s Reference Guide for some possible connection di...

Page 39: ...ters Refer to Appendix D for the environment parameters System Considerations The MVME177 draws power from both P1 and P2 of the VMEbus backplane P2 is also used for the upper 16 bits of data for 32 bit transfers and for the upper 8 address lines for extended addressing mode The MVME177 will not operate properly unless its main board is connected to P1 and P2 of the VMEbus backplane Whether the MV...

Page 40: ... may be configured into a single VME card cage In general hardware multiprocessor features are supported Other MPUs on the VMEbus can Interrupt Disable Communicate with and Determine the operational status of the processor s One register of the GCSR set includes four bits which function as location monitors to allow one MVME177 processor to broadcast a signal to other MVME177 processors if any All...

Page 41: ...nator power through a diode and a 1 amp polyswitch F1 located on the P2 Adapter Board If the polyswitch is blown i e open the SCSI devices may not operate or may function erratically When the P2 Adapter Board is used with an MVME712M and the SCSI bus is connected to the MVME712M the green LED DS2 on the MVME712M front panel lights when there is SCSI terminator power If the LED flickers during SCSI...

Page 42: ...Hardware Preparation and Installation 2 18 2 ...

Page 43: ...lowing ABORT and RESET switches FAIL STAT RUN SCON LAN 12V LAN power SCSI and VME indicators ABORT Switch S1 When enabled by software the recessed front panel ABORT switch generates an interrupt at a user programmable level It is normally used to abort program execution and return to the 177Bug debugger firmware located in the MVME177 EPROMs The ABORT switch interrupter in the VMEchip2 is an edge ...

Page 44: ...generated by the following RESET switch Power up reset Watchdog timeout Control bit in the LCSR SYSRESET remains asserted for at least 200 msec as required by the VMEbus specification Similarly the VMEchip2 provides an input signal and a control bit to initiate a local reset operation By setting a control bit software can maintain a board in a reset state disabling a faulty board from participatin...

Page 45: ... is low This indicates one of the local bus masters is executing a local bus cycle The green SCON LED part of DS2 lights when the VMEchip2 in the MVME177 is the VMEbus system controller The green LAN LED part of DS3 lights when the LAN chip is local bus master The MVME177 supplies 12V power to the Ethernet transceiver interface through a fuse The green 12V LAN power LED part of DS3 lights when pow...

Page 46: ...MVME177s on the same VMEbus with different virtual local bus maps as viewed by different VMEbus masters Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined by the Transfer Type TT signals on the local bus On the MVME177 Transfer Types 0 1 and 2 define the normal address range Table 3 1 Local Bu...

Page 47: ... EPROM memory is mapped at 00000000 through 003FFFFF by hardware default through the VMEchip2 Table 3 1 Local Bus Memory Map Address Range Devices Accessed Port Size Size Software Cache Inhibit Notes 00000000 DRAMSIZE User programmable onboard ECC DRAM on mezzanine D32 DRAMSIZE N 1 2 DRAMSIZE FF7FFFFF User programmable VMEbus A32 A24 D32 D16 3GB 3 4 FF800000 FFBFFFFF EPROM Flash D32 1MB EPROM 4MB ...

Page 48: ... 3 2 Local I O Devices Memory Map Address Range Devices Accessed Port Size Size Notes FFF00000 FFF3FFFF Reserved 256KB 5 FFF40000 FFF400FF VMEchip2 LCSR D32 256B 1 4 FFF40100 FFF401FF VMEchip2 GCSR D32 D8 256B 1 4 FFF40200 FFF40FFF Reserved 3 5KB 5 7 FFF41000 FFF41FFF Reserved 4KB 5 FFF42000 FFF42FFF PCCchip2 D32 D8 4KB 1 FFF43000 FFF430FF MCECC 1 D8 256B 1 FFF43100 FFF431FF MCECC 2 D8 256B 1 FFF4...

Page 49: ...CSR in the VMEchip2 must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits 5 This area does not return an acknowledge signal If the local bus timer is enabled the access times out and terminates by a TEA signal 6 This area does return an acknowledge signal 7 Size is approximate FFF77000 FFF...

Page 50: ...ackage set up the default values of many of these registers Specific programming details may be determined by study of the M68060 Microprocessor User s Manual You can also check the details of all the MVME177 onboard registers as given in the Single Board Computers Programmer s Reference Guide Multi MPU Programming Considerations Good programming practice dictates that only one MPU at a time has c...

Page 51: ...RESET When the local bus reset signal is asserted a local bus cycle may be aborted The VMEchip2 is connected to both the local bus and the VMEbus and if the aborted cycle is bound for the VMEbus erratic operation may result Communications between the local processor and a VMEbus master should use interrupts or mailbox locations reset should not be used in normal communications Reset should be used...

Page 52: ...Operating Instructions 3 10 3 ...

Page 53: ... are given in the Single Board Computers Programmer s Reference Guide Refer to it for the rest of the functional description of the MVME177 module MVME177 Functional Description The MVME177 is a high functionality VMEbus single board computer designed around the MC68060 chip The MVME177 has 4 8 16 32 64 128 256MB of dynamic RAM SCSI mass storage interface Four serial ports One parallel port Ethern...

Page 54: ...2596CA LAN CD2401 serial through the PCCchip2 53C710 SCSI VMEbus MPU In the general case any master can access any slave however not all combinations pass the common sense test Refer to the Single Board Computers Programmer s Reference Guide and to the user s guide for each device to determine Port size Data bus connection Any restrictions that apply when accessing the device ...

Page 55: ...processor CD2401 Quad Serial I O Controller 128KB SRAM w battery option MC68060 MPU 50 or 60 MHZ 4MB FLASH Address MUX Data MUX Control PCC2 ASIC Parallel I O Port Centronics DS1643 or MK48T08 Battery Backed 8KB RAM Clock 4 to 256MB ECC DRAM 1818 9604 VMEbus A32 24 D64 32 16 08 Master Slave Ethernet Transceiver SCSI Peripherals 4 Asynchronous or 3 Async 1 Sync ...

Page 56: ...ssor bus runs at only half the processor speed Refer to the MC68060 user s manual for more information Flash Memory and EPROM Flash Memory The MVME177 includes four 28F008SA Flash memory devices The Flash devices provide 4MB of ROM at address FF800000 FFBFFFFF The Flash is organized as one 32 bit bank for 32 bit code execution from the processor The Flash could for instance be used for the onboard...

Page 57: ...PIO2 bit Because the MVME177 uses 1M x 8 bit Flash memory devices and EPROMs with no download ROM the software programs the VMEchip2 ROM0 and REV EROM bits properly so that the Flash EPROM appears at address 0 after powerup The hardware is implemented so that the EPROM Flash appears at address 00000000 following a local bus reset Table 4 1 EPROM and Flash Control and Configuration Jumper or Contro...

Page 58: ...e up only 1MB of memory but can share the first 2MB of space with the first 2MB of Flash The EPROMs occupy only 1MB space in the ROM space in mixed mode and will be repeated in the second 1MB space which is reserved for future expansion The EPROMs could coexist with this 2MB of Flash or could be used to program all 4MB of Flash then the J8 jumper could be removed to make only Flash available After...

Page 59: ...he SRAM allows the debugger to operate and limited diagnostics to be executed without the DRAM mezzanine The SRAM will not support burst cycles The SRAM is controlled by the VMEchip2 and the access time is programmable Refer to the VMEchip2 in the Single Board Computers Programmer s Reference Guide for more detail The boards are populated with 100 ns SRAMs SRAM battery backup is optionally availab...

Page 60: ... 50 the board is powered on half of the time the battery lifetime is four years At lower ambient temperatures the backup time is greatly extended and may approach the shelf life of the battery When a board is stored if the battery is present it should be disconnected to prolong battery life This is especially important at high ambient temperatures MVME177 boards with battery backup are shipped wit...

Page 61: ...the module carefully pull the battery from the socket Onboard DRAM The MVME177 onboard DRAM is located on a mezzanine board The mezzanine boards use error checking and correction ECC protection to correct single bit errors and detect double bit errors Interrupts or bus exception can be enabled when a bit error is detected The interrupt output from the memory mezzanine is connected to the VMEchip2 ...

Page 62: ...cessed Refer to the MCECC in the Single Board Computers Programmer s Reference Guide for detailed programming information Most DRAM devices require some number of access cycles before the DRAMs are fully operational Normally this requirement is met by the onboard refresh circuitry and normal DRAM initialization However software should insure a minimum of 10 initialization cycles are performed to e...

Page 63: ...oard Computers Programmer s Reference Guide and to the DS1643 MK48T08 data sheet for detailed programming information VMEbus Interface The local bus to VMEbus interface the VMEbus to local bus interface and the local VMEbus DMA controller functions on the MVME177 are provided by the VMEchip2 The VMEchip2 can also provide the VMEbus system controller functions Refer to the VMEchip2 in the Single Bo...

Page 64: ... rates 110 to 38 4K baud The four serial ports are different functionally because of the limited number of pins on the P2 I O connector Serial port 1 is a minimum function asynchronous port It uses RXD CTS TXD RTS Serial ports 2 and 3 are full function asynchronous ports They use RXD CTS DCD TXD RTS DTR Serial port 4 is a full function asynchronous or synchronous port It can operate at synchronous...

Page 65: ...ties the DTR signal from the CD2401 to the pin labeled RTS at connector P2 Likewise RTS from the CD2401 is tied to DTR on P2 Therefore when programming the CD2401 assert DTR when you want RTS and RTS when you want DTR The interface provided by the PCCchip2 allows the 16 bit CD2401 to appear at contiguous addresses however accesses to the CD2401 must be 8 or 16 bits 32 bit accesses are not permitte...

Page 66: ... port may be used as a Centronics compatible parallel printer port or as a general parallel I O port When used as a parallel printer port the five status pins function as Printer Acknowledge ACK Fault FAULT Busy BSY Select SELECT Paper Error PE The control pins act as Printer Strobe STROBE Input Prime INP The PCCchip2 provides an auto strobe feature similar to that of the MVME147 PCC In auto strob...

Page 67: ... an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector In addition the six bytes including the Ethernet address are stored in the configuration area of the BBRAM That is 08003E2xxxxx is stored in the BBRAM At an address of FFFC1F2C the upper four bytes 08003E2x can be read At an address of FFFC1F30 the lower two bytes xxxx can be read Refer to the BBRAM TOD Clock mem...

Page 68: ...Cchip2 Refer to the 53C710 user s guide and to the Single Board Computers Programmer s Reference Guide for detailed programming information SCSI Termination The system configurer must ensure that the SCSI bus is properly terminated at both ends On the MVME177 sockets are provided for the terminators on the P2 transition board If the SCSI bus ends at the P2 transition board then termination resisto...

Page 69: ...for detailed programming information Watchdog Timer A watchdog timer function is provided in the VMEchip2 When the watchdog timer is enabled it must be reset by software within the programmed time or it times out The watchdog timer can be programmed to generate A SYSRESET signal Local reset signal or Board fail signal if it times out Refer to the VMEchip2 in the Single Board Computers Programmer s...

Page 70: ... Reference Guide for detailed programming information Module Identification Software distinguishes between an MVME177 module and an MVME176 module by use of the I O control register GPI bit 3 On an MVME177 the I O control register GPI bit 3 is out open for a ÒhighÓ one On an MVME176 the I O control register GPI bit 3 is hardwired in shorted for a ÒlowÓ zero Timing Performance This section provides...

Page 71: ...face with DMA controller The SCSI DMA controller uses a FIFO buffer to interface the 8 bit SCSI bus to the 32 bit local bus The FIFO buffer allows the SCSI DMA controller to efficiently transfer data to the local bus in four longword bursts This reduces local bus usage by the SCSI device The first longword transfer of a burst with snooping disabled requires Four bus clocks with parity off and Five...

Page 72: ...ler is 20MB sec at 25 MHz or 24MB sec at 30 MHz with parity off Assuming a continuous transfer rate of 1MB sec on the LAN bus 5 or 4 of the local bus bandwidth is used by transfers from the LAN bus Remote Status and Control The remote status and control connector J3 is a 20 pin connector located behind the front panel of the MVME177 It provides system designers the flexibility to access critical i...

Page 73: ...urpose Although handshaking is unnecessary in many applications the lines themselves remain part of many designs because they facilitate troubleshooting Table A 1 lists the standard EIA 232 D interconnections To interpret this information correctly remember that EIA 232 D was intended to connect a terminal to a modem When computers are connected to each other without modems one of them must be con...

Page 74: ...age transmission can begin When a modem is used CTS follows the off to on transition of RTS after a time delay 06 DSR DATA SET READY Output from the modem to the terminal to indicate that the modem is ready to transmit data 07 SIG GND SIGNAL GROUND Common return line for all signals at the modem interface 08 DCD DATA CARRIER DETECT Output from the modem to the terminal to indicate that a valid car...

Page 75: ...es and a ground The full implementation of EIA 232 D requires 12 lines it accommodates Automatic dialing Automatic answering Synchronous transmission A middle of the road approach is illustrated in Figure A 1 22 RI RING INDICATOR Output from the modem to the terminal indicates to the terminal that an incoming call is present The terminal causes the modem to answer the phone by carrying DTR true wh...

Page 76: ...e of this signal was to inform the system that the carrier tone from the distant modem was being received This signal is frequently used by the software to display a message like CARRIER NOT PRESENT to help the user to diagnose failure to communicate Obviously if the system is designed properly to use this signal and is not connected to a modem the signal must be provided by a pullup resistor or g...

Page 77: ... DCD TXC RXC OPTIONAL HARDWARE TRANSPARENT MODE LOGIC 470Ω 39kΩ 39kΩ 39kΩ 470Ω 39kΩ 12V 2 1 5 6 8 7 7 1 20 2 3 4 5 6 CHASSIS GND CONNECTOR TO TERMINAL CONNECTOR TO MODEM OR HOST SYSTEM RXD TXD NC CTS DSR DCD SIG GND DTR TXD RXD RTS CTS DCD 12V 12V 12V 12V 12V GND 12V SIG GND NC cb181 9210 470Ω 6850 6850 LS08 LS08 470Ω 470Ω 470Ω MODULE ...

Page 78: ...TS DCD and DSR signals Two of these connectors wired back to back can be used In this implementation however diagnostic messages that might otherwise be generated do not occur because all the handshaking is bypassed In addition the TX and RX lines may have to be crossed since TX from a terminal is outgoing but the TX line on a modem is an incoming signal Figure A 2 Minimum EIA 232 D Connection GND...

Page 79: ...e connected to different electrical outlets there may be several volts of difference in ground potential If pin 1 of each device is interconnected with the others via cable several amperes of current could result This condition may not only be dangerous for the small wires in a typical cable but may also produce electrical noise that causes errors in data transmission That is why Figure A 1 shows ...

Page 80: ...EIA 232 D Interconnections A 8 A ...

Page 81: ... family is implemented on the MVME177 Single Board Computer and is known as the MVME177Bug or simply 177Bug Description of 177Bug The 177Bug package is a powerful evaluation and debugging tool for systems built around the MVME177 CISC based microcomputers Facilities are available for loading and executing user programs under complete operator control for system evaluation 177Bug includes Commands ...

Page 82: ...gnostic prompt Ò177 Diag Ó displays and you have all of the diagnostic commands at your disposal as well as all of the debugger commands You may switch between directories by using the Switch Directories SD command or may examine the commands in the particular directory that you are currently in by using the Help HE command Because 177Bug is command driven it performs its various operations in res...

Page 83: ... result which includes a pre calculated checksum contained in the EPROMs is tested for an expected zero Thus users are cautioned against modification of the EPROMs unless re checksum precautions are taken The power on defaults for the MVME177 debug port are Eight bits per character One stop bit per character Parity disabled no parity Baud rate 9600 baud default baud rate of MVME177 ports at power ...

Page 84: ...tunity to abort the Autoboot process if you wish Then the actual I O begins the program pointed to within the volume ID of the media specified loads into RAM and control passes to it If however during this time you want to gain control without Autoboot you can press the BREAK key Software ABORT switch RESET switch Autoboot is controlled by parameters contained in the ENV command These parameters a...

Page 85: ...onally By the RB command assuming there is valid code in the EPROMs or optionally elsewhere on the module or VMEbus to support it If ROMboot code is installed a user written routine is given control if the routine meets the format requirements One use of ROMboot might be resetting SYSFAIL on an unintelligent controller module The NORB command disables the function For a user s ROMboot module to ga...

Page 86: ...e until a valid bootable device containing a boot media is found or the list is exhausted If a valid bootable device is found a boot from that device begins The controller scanning sequence goes from the lowest controller Logical Unit Number LUN detected to the highest LUN detected At power up Network Boot is enabled and providing the drive and controller numbers encountered are valid the followin...

Page 87: ... the System You can initialize the system to a known state in three different ways Reset Abort Break Each has characteristics which make it more appropriate than the others in certain situations The debugger has a special feature upon a reset condition This feature is activated by depressing the RESET and ABORT switches at the same time This feature instructs the debugger to use the default setup ...

Page 88: ...nput and output character queues are cleared Onboard devices timer serial ports etc are reset The first two serial ports are reconfigured to their default state During WARM reset the 177Bug preserves the following Variables Tables Target state registers Breakpoints Reset must be used if the processor ever halts or if the 177Bug environment is ever lost vector table is destroyed stack corrupted etc...

Page 89: ...ble remains intact Control returns to the debugger Break You can generate a ÒBreakÓ by pressing and releasing the BREAK key on the terminal keyboard Break does not generate an interrupt The only time break is recognized is when characters are sent or received by the console port A Break causes All breakpoints in your code to be removed Breakpoint table to be maintained intact A snapshot to be take...

Page 90: ... of the above situations have occurred the SYSFAIL line is negated This indicates to the user or VMEbus masters the state of the debugger In a multi computer configuration other VMEbus masters could view the pertinent control and status registers to determine which CPU is asserting SYSFAIL SYSFAIL assertion negation is also affected by the ENV command MPU Clock Speed Calculation The clock speed of...

Page 91: ...ere this block of memory is located Regardless of where the onboard RAM is located the first 64KB is used for 177Bug stack and static variable space and the rest is reserved as user space Whenever the MVME177 is reset Target PC is initialized to the address corresponding to the beginning of the user space Target stack pointers are initialized to addresses within the user space Target Interrupt Sta...

Page 92: ... port is conÞgured with the hardcopy or TTY option refer to PF command then a carriage return and line feed is issued along with another prompt H backspace The cursor is moved back one position The character at the new cursor position is erased If the hardcopy option is selected a Ò Ó character is typed along with the deleted character D redisplay The entire command line as entered so far is redis...

Page 93: ...disk parameters Parameters such as Address where the module is mapped Device type Number of devices attached to the controller module are kept in tables by 177Bug Default values for these parameters are assigned at power up and cold start reset but may be altered as described in the section on default parameters later in this chapter Blocks Versus Sectors The logical block defines the unit of info...

Page 94: ... 14 B The sector defines the unit of information for the media itself as viewed by the controller The sector size varies for different controllers and the value for a specific device can be displayed and changed with the IOT command ...

Page 95: ...to the controller to initiate the transfer If the conversion from blocks to sectors yields a fractional sector count an error is returned and no data is transferred Device Probe Function A device probe with entry into the device descriptor table is performed whenever a specified device is accessed i e when system calls DSKRD DSKWR DSKCFIG DSKFMT DSKCTRL or debugger commands BH BO IOC IOP IOT MAR M...

Page 96: ... in the Debugging Package for Motorola 68K CISC CPUs User s Manual When a command is issued to a particular controller LUN and device LUN these LUNs are remembered by 177Bug so that the next disk command defaults to use the same controller and device IOI Input Output Inquiry This command probes the system for all possible CLUN DLUN combinations and displays inquiry data for devices which support i...

Page 97: ...o memory then transfers control to it BH Bootstrap and Halt BH reads an operating system or control program from a specified device into memory then returns control to 177Bug It is used as a debugging tool Disk I O via 177Bug System Calls All operations that actually access the disk are done directly or indirectly by 177Bug TRAP 15 system calls The command level disk operations provide a convenien...

Page 98: ...ice Refer to the system call descriptions in the Debugging Package for Motorola 68K CISC CPUs User s Manual for details on the format and construction of these standardized ÒuserÓ packets The packets which a controller module expects to receive vary from controller to controller The disk driver module for the particular hardware module board must take the standardized packet given to a trap functi...

Page 99: ...nfiguration area This is a temporary change If a cold start reset occurs then the default parameter information is written back into the tables Using the IOT You can use this command to reconfigure the parameter table manually for any controller and or device that is different from the default This is also a temporary change and is overwritten if a cold start reset occurs Obtain the source You can...

Page 100: ...ement is in the scope of Reception of packets Transmission of packets Receive buffer flushing Interface initialization This module ensures that the packaging and unpackaging of Ethernet packets is performed correctly in the Boot PROM UDP IP Protocol Modules The Internet Protocol IP is designed for use in interconnected systems of packet switched computer communication networks The Internet protoco...

Page 101: ...dresses e g Ethernet addresses The RARP protocol module supports systems which do not support the BOOTP protocol next paragraph BOOTP Protocol Module The Bootstrap Protocol BOOTP basically allows a diskless client machine to discover Its own IP address The address of a server host The name of a file to be loaded into memory and executed TFTP Protocol Module The Trivial File Transfer Protocol TFTP ...

Page 102: ...cessful Multiprocessor Support The MVME177 dual port RAM feature makes the shared RAM available to remote processors as well as to the local processor This can be done by either of the following two methods Either method can be enabled disabled by the ENV command as its Remote Start Switch Method Multiprocessor Control Register MPCR Method A remote processor can initiate program execution in the l...

Page 103: ...sed for multi processor support 800 through 807 The MPCR contains 00 at power up indicating that initialization is not yet complete As the initialization proceeds the execution path comes to the ÒpromptÓ routine Before sending the prompt this routine places an R in the MPCR to indicate that initialization is complete Then the prompt is sent If no terminal is connected to the port the MPCR is still...

Page 104: ...CSR Method A remote processor can initiate program execution in the local MVME177 dual port RAM by issuing a remote GO command using the VMEchip2 Global Control and Status Registers GCSR The remote GO command causes the following sequence Remote processor places the MVME177 execution address in general purpose registers 0 and 1 GPCSR0 and GPCSR1 Remote processor sets bit 8 SIG0 of the VMEchip2 LM ...

Page 105: ... that you are currently in by using the HE Help command If you are in the debugger directory the debugger prompt 177 Bug displays and all of the debugger commands are available Diagnostics commands cannot be entered at the 177 Bug prompt If you are in the diagnostic directory the diagnostic prompt 177 Diag displays and all of the debugger and diagnostic commands are available The diagnostic test g...

Page 106: ...agnostic Test Groups Test Group Description RAM Local RAM Tests SRAM Static RAM Tests RTC MK48T0x Real Time Clock Tests PCC2 Peripheral Channel Controller Tests MCECC Memory Board Tests MEMC1 MC040 Memory Controller 1 ASIC Tests MEMC2 MC040 Memory Controller 2 ASIC Tests ST2401 CD2401 Serial Port Tests CMMU Cache and Memory Management Unit Tests VME2 VME Interface ASIC VMEchip2 Tests LANC LAN Copr...

Page 107: ... execution of user target code for example GO then control may or may not return to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the TRAP 15 function Ò RETURNÓ In gen...

Page 108: ... to be replaced by one of a class of items it represents A vertical bar separating two or more items indicates that a choice is to be made only one of the items separated by this symbol should be selected Square brackets enclose an item that is optional The item may appear zero or one time Braces enclose an optional symbol that may occur zero or more times DEL Delimiter either a comma or a space E...

Page 109: ...ical AND Shift left Shift right Numeric values may be expressed in either Hexadecimal Decimal Octal Binary by immediately preceding them with the proper base identifier If no base identifier is specified then the numeric value is assumed to be hexadecimal Data Type Base IdentiÞer Examples Integer Hexadecimal FFFFFFFF Integer Decimal 1974 10 4 Integer Octal 456 Integer Binary 1000110 ...

Page 110: ...ormed according to the following rules Always from left to right unless parentheses are used to group part of the expression There is no operator precedence Subexpressions within parentheses are evaluated first Nested parenthetical subexpressions are evaluated from the inside out Valid expression examples The total value of the expression must be between 0 and FFFFFFFF String Literal Numeric Value...

Page 111: ...ess contents of automatic offset register N Rn 130 R5 Absolute address contents of the speciÞed offset register not an assembler accepted syntax An A1 Address register indirect also post increment predecrement d An or d An 120 A1 120 A1 Address register indirect with displacement two formats accepted d An Xn or d An Xn 120 A1 D2 120 A1 D2 Address register indirect with index and displacement two f...

Page 112: ...am The offset registers solve this problem by taking into account this difference and forcing the display of addresses in a relative address offset format Offset registers have adjustable ranges and may even have overlapping ranges The range for each offset register is set by two addresses Base Top Specifying the base and top addresses for an offset register sets its range In the event that an add...

Page 113: ...11 0 00000010 4CDF0101 MOVEM L A7 D0 A0 12 0 00000014 4E75 RTS 13 14 END TOTAL ERRORS 0 TOTAL WARNINGS 0 The above program was loaded at address 0001327C The disassembled code is shown next 177Bug MD 1327C DI 0001327C 48E78080 MOVEM L D0 A0 A7 00013280 4280 CLR L D0 00013282 1018 MOVE B A0 D0 00013284 5340 SUBQ W 1 D0 00013286 12D8 MOVE B A0 A1 00013288 51C8FFFC DBF D0 13286 0001328C 4CDF0101 MOVE...

Page 114: ...you the option of choosing the port to be used to input or output Valid port numbers which may be used for these commands are as follows 1 MVME177 EIA 232 D Debug Terminal Port 0 or 00 PORT 1 on the MVME177 P2 connector Sometimes known as the Òconsole portÓ it is used for interactive user input output by default 2 MVME177 EIA 232 D Terminal Port 1 or 01 PORT 2 on the MVME177 P2 connector Sometimes...

Page 115: ...st system The program must be in S record format described in the Debugging Package for Motorola 68K CISC CPUs User s Manual and may have been assembled or compiled on the host system Alternately the program may have been previously created using the 177Bug MM command as outlined above and stored to the host using the Dump DU command A communication link must exist between the host system and the ...

Page 116: ...ontain temporary variables exception vectors etc If you disturb resources upon which 177Bug depends then the debugger may function unreliably or not at all If your application enables translation through the Memory Management Units MMUs and if your application utilizes resources of the debugger e g system calls your application must create the necessary translation tables for the debugger to have ...

Page 117: ...nter PC causing a system crash Hardware Functions The only hardware resources used by the debugger are the EIA 232 D ports which are initialized to interface to the debug terminal If these ports are reprogrammed the terminal characteristics must be modified to suit or the ports should be restored to the debugger set characteristics prior to reinvoking the debugger Exception Vectors Used by 177Bug ...

Page 118: ... 0 F0 CACR 0 D0 00000001 D1 00000000 D2 00000000 D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 0000FFFC 00010006 D280 ADD L D0 D1 177Bug Table B 3 Exception Vectors Used by 177Bug Vector Offset Exception 177Bug Facility 10 Illegal instruction Breakpoints used by GO GN GT 24 Trace Trace operations s...

Page 119: ...is address loads into the target state VBR at power up or cold start reset and can be observed by using the RD command to display the target state registers immediately after power up The 177Bug initializes the target vector table with the debugger vectors listed in Table B 3 and fills the other vector locations with the address of a generalized exception handler refer to the 177Bug Generalized Ex...

Page 120: ... is not used This provides diagnostic support in the event that your program is stopped by an unexpected exception The generalized exception handler gives a formatted display of the target registers and identifies the type of the exception The following is an example of a routine which builds a separate vector table and then moves the VBR to point at it BUILDX Build exception vector table BUILDX M...

Page 121: ...tor location which is the address of the 177Bug exception handler Your program must make sure that there is an exception stack frame in the stack and that it is exactly the same as the processor would have created for the particular exception before jumping to the address of the exception handler The following is an example of an exception handler which can pass an exception along to the debugger ...

Page 122: ...k pointer is left pointing to the top of the exception stack frame created In this way if an unexpected exception occurs during execution of your code you are presented with the exception stack frame to help determine the cause of the exception The following example illustrates this Example Bus error at address F00000 It is assumed for this example that an access of memory location F00000 initiate...

Page 123: ...8 TR OFF_S _7_ N VBR 00000000 USP 0000DFFC MSP 0000EFFC ISP 0000FFFC SFC 0 F0 DFC 0 F0 CACR 0 D0 00000001 D1 00000001 D2 00000000 D3 00000000 D4 00000000 D5 00000002 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 0000FFC0 00010000 203900F0 0000 MOVE L F00000 L D0 177Bug Notice that the target stack pointer is different The target stac...

Page 124: ...assembled disassembled with the DI option of the MD and MM commands Valid data types that can be used when modifying a floating point data register or a floating point memory location Integer Data Types 12 Byte 1234 Word 12345678 Longword Floating Point Data Types 1_FF_7FFFFF Single Precision Real Format 1_7FF_FFFFFFFFFFFFF Double Precision Real Format 1_7FFF_FFFFFFFFFFFFFFFF Extended Precision Re...

Page 125: ...ecimal field 4 The sign field the exponent field and at least the first digit of the mantissa field must be present any unspecified digits in the mantissa field are set to zero 5 Each field must be separated from adjacent fields by an underscore 6 All the digit positions in the sign and exponent fields must be present Single Precision Real This format would appear in memory as A single precision n...

Page 126: ...extended precision number requires 10 bytes in memory Packed Decimal Real This format would appear in memory as A packed decimal number requires 12 bytes in memory 1 bit sign Þeld 1 binary digit 11 bit biased exponent Þeld 3 hex digits Bias 3FF 52 bit fraction Þeld 13 hex digits 1 bit sign Þeld 1 binary digit 15 bit biased exponent Þeld 4 hex digits Bias 3FFF 64 bit mantissa Þeld 16 hex digits 4 b...

Page 127: ... Ð An optional underscore Ð The Exponent field identifier letter ÒEÓ Ð An optional Exponent sign Ð From 1 to 3 decimal digits For more information about the MC68060 floating point unit refer to the MC68060 Microprocessor User s Manual Additions to FLASH Commands The 4MB of Flash memory on the MVME177 is unique in the way that the lower half ÒshadowsÓ the PROM space in the memory map A jumper on th...

Page 128: ...hrough FF Test Data Increment Decrement Step 00000001 0 1 2 F 1 etc 177 Bug sd 177 Diag he flash FLASH Flash Memory Tests DIR TESTS ERASE Erase FILL Fill PATS Patterns Erase Test The erase test erases Flash memory according to the current test configuration parameters selecting starting and ending blocks Command Input 177 Diag flash erase Flash Fill Test This test executes on the i28f008sa FLASHFI...

Page 129: ...ta patterns in Flash memory according to the current test configuration parameters selecting starting and ending blocks and saving restoring of the Flash contents Note If you are running the Flash test and 177Bug itself resides in Flash the test will fail as shown in the example below Command Input 177 Diag flash pats 177 Bug sd 177 Diag flash FLASH TESTS Running FAILED FLASH TESTS Test Failure Da...

Page 130: ... argument to the PFLASH command may be specified in two ways A relative offset into the Flash memory array Ð 0 the bottom or lowest possible Flash memory array location Ð 3FFFFF the top location or end of the Flash memory array An equivalent to the physical address that will apply when the entire Flash is mapped in as when J8 is removed Ð FF800000 the bottom or lowest possible Flash memory array l...

Page 131: ...on the same destination starting address that was entered This happens because the PFLASH command is needed to switch the portion of the Flash that is visible in order to program it If switching is required the map will be restored to the condition that existed before PFLASH was entered SFLASH Command A new command is added to the 177BUG to assist the user in accessing the 4MB Flash memory array H...

Page 132: ...ed It also allows programming the entire 4MB of flash or any portion with a single PFLASH command Assuming J8 is installed then for this command sequence sflash l pflash ff800000 ff9fffff ffa00000 The SFLASH L command has no effect on the destination address used by the PFLASH command It is only a convenient way for the user to change which portion of the Flash memory array is in view In this case...

Page 133: ...ASH command consult the Debugging Package for Motorola 68K CISC CPUs UserÕs Manual The 177Bug Debugger Command Set The 177Bug debugger commands are summarized in Table B 4 HE is the 177Bug help facility HE CR displays only the command names of all available commands along with their appropriate titles HE COMMAND displays The command name Title for that particular command Complete command syntax Th...

Page 134: ...O DEL Controller LUN DEL Device LUN DEL String BR Breakpoint Insert BR ADDR COUNT NOBR Breakpoint Delete NOBR ADDR BS Block of Memory Search BS RANGE DEL TEXT B W L or BS RANGE DEL data DEL mask B W L N V BV Block of Memory Verify BV RANGE DEL data increment B W L CM Concurrent Mode CM PORT DEL ID STRING DEL BAUD DEL PHONE NUMBER A H NOCM No Concurrent Mode NOCM CNFG ConÞgure Board Information Blo...

Page 135: ...T A F H T IRQM Interrupt Request Mask IRQM MASK LO Load S records from Host LO n ADDR X C T text MA Macro DeÞne Display MA NAME L NOMA Macro Delete NOMA NAME MAE Macro Edit MAE name line string MAL Enable Macro Expansion Listing MAL NOMAL Disable Macro Expansion Listing NOMAL MAW Save Macros MAW controller LUN DEL device LUN DEL block MAR Load Macros MAR controller LUN DEL device LUN DEL block MD ...

Page 136: ...OC Network I O Control NIOC NIOP Network I O Physical NIOP NIOT Network I O Teach NIOT H A NPING Network Ping NPING Controller LUN Device LUN Source IP Destination IP N Packets OF Offset Registers Display Modify OF Rn A PA Printer Attach PA n NOPA Printer Detach NOPA n PF Port Format PF PORT NOPF Port Detach NOPF PORT PFLASH Load FLASH Memory PFLASH SSADDR SEADDR DSADDR IEADDR A R X PFLASH SSADDR ...

Page 137: ... L U SYM Symbol Table Attach SYM ADDR NOSYM Symbol Table Detach NOSYM SYMS Symbol Table Display Search SYMS symbol name S T Trace T COUNT TA Terminal Attach TA port TC Trace on Change of Control Flow TC count TIME Display Time and Date TIME C L O TM Transparent Mode TM n ESCAPE TT Trace to Temporary Breakpoint TT ADDR VE Verify S Records Against Memory VE n ADDR X C text VER Display Revision Versi...

Page 138: ...Debugger General Information B 58 B ...

Page 139: ...ddress and can be called up by Second CLUN Controller Type First CLUN First Address Second CLUN Second Address CISC Single Board Computer SBC 00 Note 1 MVME320 Winchester Floppy Controller 11 Note 2 FFFFB000 12 Note 2 FFFFA000 MVME323 ESDI Winchester Controller 08 FFFFA000 09 FFFFA200 MVME327A SCSI Controller 02 FFFFA600 03 FFFFA700 MVME328 SCSI Controller 06 FFFF9000 07 FFFF9800 MVME328 SCSI Cont...

Page 140: ... Four Devices Controller LUN Address Device LUN Device Type 0 xxxxxxxx 00 10 20 30 40 50 60 SCSI Common Command Set CCS which may be any of these Fixed direct access Removable ßexible direct access TEAC style CD ROM Sequential access Controller LUN Address Device LUN Device Type 11 FFFFB000 0 1 2 3 Winchester hard drive Winchester hard drive 5 1 4 DS DD 96 TPI ßoppy drive 12 FFFFAC00 5 1 4 DS DD 9...

Page 141: ...hard drive ESDI Winchester hard drive ESDI Winchester hard drive 9 FFFFA200 ESDI Winchester hard drive Controller LUN Address Device LUN Device Type 2 FFFFA600 00 10 20 30 40 50 60 SCSI Common Command Set CCS which may be any of these Fixed direct access Removable ßexible direct access TEAC style CD ROM Sequential access 3 FFFFA700 80 81 Local ßoppy drive Local ßoppy drive ...

Page 142: ...CS which may be any of these Removable ßexible direct access TEAC style CD ROM Sequential access 7 FFFF9800 16 FFFF4800 40 48 50 58 60 68 70 Same as above but these will only be available if the daughter card for the second SCSI channel is present 17 FFFF5800 18 FFFF7000 19 FFFF7800 Controller LUN Address Device LUN Device Type 4 FFFF5000 0 QIC 02 streaming tape drive 5 FFFF5100 ...

Page 143: ...Sector Size 0 128 1 256 2 512 3 1024 4 2048 5 4096 1 2 2 2 2 2 2 Block Size 0 128 1 256 2 512 3 1024 4 2048 5 4096 1 1 1 1 1 1 1 Sectors Track 10 8 9 9 F 12 24 Number of Heads 2 2 2 2 2 2 2 Number of Cylinders 50 28 28 50 50 50 50 Precomp Cylinder 50 28 28 50 50 50 50 Reduced Write Current Cylinder 50 28 28 50 50 50 50 Step Rate Code 0 0 0 0 0 0 0 Single Double DATA Density D D D D D D D Single Do...

Page 144: ...0 2D00 Number of Bytes in Decimal 653312 327680 368460 737280 1228800 1474560 2949120 Media Size Density 5 25 DD 5 25 DD 5 25 DD 3 5 DD 5 25 D 3 5 HD 3 5 ED Notes 1 All numerical parameters are in hexadecimal unless otherwise noted 2 The DSDD5 type ßoppy is the default setting for the debugger IOT Parameter Floppy Types and Formats Continued DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT PS2 SHD ...

Page 145: ...rd information block Lists the size of each element Lists the logical offset of each element The CNFG command does not describe the elements and their use The board information block contents are checksummed for validation purposes This checksum is the last element of the block Example to display the current contents of the board information block 177 Bug cnfg Board PWA Serial Number 000000061050 ...

Page 146: ...G Board Information Block Checksum Error is also displayed in the event of a checksum failure Using the I option initializes the unused area of the board information block to zero Modification is permitted by using the M option of the command At the end of the modification session you are prompted for the update to Non Volatile RAM NVRAM A YÓ response must be made for the update to occur any other...

Page 147: ...user to invoke the ENV command Once the ENV command is invoked and executed without error Bug default and or user parameters are loaded into NVRAM along with checksum data If any of the operational parameters have been modified these new parameters will not be in effect until a reset powerup condition If the ENV command is invoked with no options on the command line you are prompted to configure a...

Page 148: ...0000000 Memory Search Ending Address 02000000 Memory Search Increment Size 00010000 Memory Search Delay Enable Y N N Memory Search Delay Address FFFFCE0F Memory Size Enable Y N Y Memory Size Starting Address 00000000 Memory Size Ending Address 02000000 Base Address of Local Memory 00000000 Size of Local Memory Board 0 02000000 Size of Local Memory Board 1 00000000 Slave Enable 1 Y N Y Slave Starti...

Page 149: ...00 Master Address Translation Select 4 00000000 Master Control 4 00 Short I O VMEbus A16 Enable Y N Y Short I O VMEbus A16 Control 01 F Page VMEbus A24 Enable Y N Y F Page VMEbus A24 Control 02 ROM Speed Bank A Code 05 ROM Speed Bank B Code 05 Static RAM Speed Code 01 PCC2 Vector Base 05 VMEC2 Vector Base 1 06 VMEC2 Vector Base 2 07 VMEC2 GCSR Group Base Address D4 VMEC2 GCSR Board Base Address 00...

Page 150: ... the bug command monitor Local SCSI Bus Reset on Debugger Startup Y N N Local SCSI bus is not reset on debugger startup Local SCSI Bus Negotiations Type A S N A Asynchronous Ignore CFGA Block on a Hard Disk Boot Y N Y Enable the ignorance of the ConÞguration Area CFGA Block hard disk only Auto Boot Enable Y N N Auto Boot function is disabled Auto Boot at power up only Y N Y Auto Boot is attempted ...

Page 151: ...ss FF800000 First location tested when the Bug searches for a ROMboot Module ROM Boot Direct Ending Address FFBFFFFC Last location tested when the Bug searches for a ROMboot Module Network Auto Boot Enable Y N N Network Auto Boot function is disabled Network Auto Boot at power up only Y N Y Network Auto Boot is attempted at power up reset only Network Auto Boot Controller LUN 00 LUN of a disk tape...

Page 152: ...C0000 through FFFC0FFF The NIOT parameters do not exceed 128 bytes in size The location for these parameters is determined by setting this ENV pointer If you have used the exact same space for your own program information or commands they will be overwritten and lost You can relocate the network interface conÞguration parameters in this space by using the ENV command to change the Network Auto Boo...

Page 153: ...e speciÞed by Memory Search Starting Address and Memory Search Ending Address parameters then the bug will place its work page in the onboard static RAM on the MVME177 Default Memory Search Ending Address is the calculated size of local memory Memory Search Increment Size 00010000 This multi CPU feature is used to offset the location of the Bug work page This must be a multiple of the debugger wor...

Page 154: ...e values before attempting to locate their work page in the memory of the primary CPU Memory Size Enable Y N Y Memory will be sized for Self Test diagnostics Memory Size Starting Address 00000000 Default Starting Address is 0 Memory Size Ending Address 02000000 Default Ending Address is the calculated size of local memory Base Address of Local Memory 00000000 Beginning address of Local Memory It m...

Page 155: ...he VMEbus address and the local address to be different The value in this register is the base address of local resource that is associated with the starting and ending address selection from the previous questions Default is 0 Slave Address Translation Select 1 00000000 This register deÞnes which bits of the address are signiÞcant A logical one 1 indicates signiÞcant address bits logical zero 0 i...

Page 156: ...rom the local bus Default is the end of calculated local memory Master Ending Address 1 EFFFFFFF Ending address of the VMEbus resource that is accessible from the local bus Default is the end of calculated memory Master Control 1 0D DeÞnes the access characteristics for the address space deÞned with this master address decoder Default is 0D Master Enable 2 Y N N Do not set up and enable the Master...

Page 157: ...ddress 4 00000000 Ending address of the VMEbus resource that is accessible from the local bus Default is 0 Master Address Translation Address 4 00000000 This register will allow the VMEbus address and the local address to be different The value in this register is the base address of VMEbus resource that is associated with the starting and ending address selection from the previous questions Defau...

Page 158: ...d to set up the SRAM speed Default 00 132 ns for 60 MHz MVME177s PCC2 chip Vector Base VMEC2 Vector Base 1 VMEC2 Vector Base 2 05 06 07 Base interrupt vector for the component speciÞed Default PCC2 chip 05 VMEchip2 Vector 1 06 VMEchip2 Vector 2 07 VMEC2 GCSR Group Base Address D4 SpeciÞes the group address FFFFxx00 in Short I O for this board Default D4 VMEC2 GCSR Board Base Address 00 SpeciÞes th...

Page 159: ...ess for each type and position is shown to indicate where the controller must reside to be supported by 177Bug The controllers are accessed via the specified CLUN and DLUNs listed here The CLUN and DLUNs are used in conjunction with the debugger commands NBH NBO NIOP NIOC NIOT NPING NAB and also with the debugger system calls NETRD NETWR NETFOPN NETFRD NETCFIG NETCTRL ...

Page 160: ...E376 03 00 FFFF1400 Ethernet MVME376 04 00 FFFF1600 Ethernet MVME376 05 00 FFFF5400 Ethernet MVME376 06 00 FFFF5600 Ethernet MVME376 07 00 FFFFA400 Ethernet MVME374 10 00 FF000000 Ethernet MVME374 11 00 FF100000 Ethernet MVME374 12 00 FF200000 Ethernet MVME374 13 00 FF300000 Ethernet MVME374 14 00 FF400000 Ethernet MVME374 15 00 FF500000 Ethernet ...

Page 161: ...ay not be getting correct power 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board per this manual 4 Check for compliance with System Considerations per this manual 5 Review the Installation and Startup procedures per this manual In most cases this includes a step by step powerup...

Page 162: ...es not free up the keyboard type in CTRL Q III Debug prompt 177 Bug does not appear at powerup and the board does not auto boot A Debugger EPROM Flash may be missing 1 Disconnect all power from your system 2 Check that the proper debugger EPROM or debugger Flash memory is installed per this manual 3 Reconnect power 4 Restart the system by Òdouble button resetÓ press the RESET and ABORT switches at...

Page 163: ...hat may affect your system operation 2 Type in env d CR This sets up the default parameters for the debugger environment 3 When prompted to Update Non Volatile RAM type in y CR 4 When prompted to Reset Local System type in y CR 5 After clock speed is displayed immediately within Þve seconds press the Return key CR or BREAK to exit to System Menu Then enter a 3 ÒGo to System DebuggerÓ and Return 3 ...

Page 164: ...isplayed If there are any errors go to step VI If there are no errors go to step V V The debugger is in system mode and the board auto boots or the board has passed selftests A No problems troubleshooting is done No further troubleshooting steps are required Note Even if the board passes all tests it may still be bad Selftest does not try out all functions in the board for example SCSI or VMEbus t...

Page 165: ...operators B 29 ASCII string B 28 assembler disassembler 1 8 B 35 assertion 1 12 autoboot B 3 B Backus Naur B 28 base and top addresses B 32 base identifier B 29 Battery Backed Up RAM BBRAM and Clock see MK48T08 and NVRAM 4 10 D 3 battery backup 4 7 battery handling and disposal 4 8 battery lifetime 4 8 BBRAM see Battery Backed Up RAM MK48T08 and NVRAM 4 10 BG bus grant 2 13 BH Bootstrap and Halt B...

Page 166: ... 1 data circuit terminating equipment DCE A 1 data terminal equipment DTE A 1 DCE data circuit terminating equip ment A 1 debug monitor see 177Bug and MVME177Bug 2 4 3 1 3 8 debug port B 34 debugger address parameter formats B 31 debugger commands B 53 B 54 debugger prompt B 27 debugging package 1 10 3 8 decimal number 1 12 default 177Bug controller and device pa rameters B 19 default baud rate 2 ...

Page 167: ...factory jumper settings 2 4 FB1225 4 8 FCC compliance 1 5 Features 1 2 features 1 5 FLASH commands B 47 flexible diskette C 2 floating point instructions B 44 floating point support B 44 floating point unit FPU B 44 B 47 floppy disk command parameters C 5 floppy diskette C 4 floppy drive C 2 C 3 forced air cooling 1 3 FPU floating point unit B 44 B 47 front panel 3 2 front panel indicators DS1 DS4...

Page 168: ... 4 15 LAN Coprocessor Ethernet Driver B 20 LAN DMA transfers 4 20 LAN FIFO buffer 4 19 LAN transceiver 2 16 LEDs 3 3 levels of implementation A 3 LFM linear feet per minute 1 3 linear feet per minute LFM 1 3 Local Area Network see LAN 4 15 local bus 4 18 local bus access 4 18 local bus memory map 3 4 3 5 local bus time out 4 18 local bus to DRAM cycle times 4 18 local I O devices memory map 3 6 lo...

Page 169: ...Controller C 1 MVME327A C 3 MVME327A SCSI Controller C 1 MVME328 C 4 MVME328 SCSI Controller C 1 MVME350 C 4 MVME374 E 2 MVME376 E 2 MVME712 12 1 6 MVME712 13 1 6 MVME712A 1 6 MVME712AM 1 6 MVME712B 1 6 MVME712M 1 6 2 12 2 17 MVME712X 1 9 2 12 4 13 N negation 1 12 network boot B 6 network boot control module B 22 network controller data E 1 network controller modules E 1 network I O error codes B ...

Page 170: ...0 4 15 SCSI FIFO buffer 4 19 SCSI interface 4 16 SCSI specification 1 10 SCSI termination 4 16 SCSI terminator power 2 17 SCSI transfers 4 19 sequential access device C 2 C 4 Serial Controller Chip SCC see CD2401 4 12 serial port 1 B 34 serial port 2 B 34 Serial Port 4 Clock Configuration Select Headers 2 8 serial port 4 clock configuration select headers J6 and J7 2 10 serial port interface 4 12 ...

Page 171: ...EM V 68 1 9 T terminal input output control B 12 terminal s A 1 terminology 1 12 TFTP protocol module B 21 Thermal Sensing Pins 2 7 thermal sensing pins 2 9 tick timers 4 17 time out 4 18 global bus 2 16 local bus 4 18 timers 4 17 timing performance 4 18 transfer type TT signals 3 4 transition modules 1 6 4 13 transparent mode A 5 TRAP 15 B 36 TT transfer type signals 3 4 U UDP IP protocol modules...

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