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C-118

MSC8101ADS RevB User’s Manual

MOTOROLA

-- with default MODCK setting from DIP-Switch
-- PONRESET pulse resets while WD.
-- Implemented as ripple counter with 30 stages

-- WDEn.s = GND; WDEn.r = GND;
-- WDEn.prn = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”10”));
-- Preset to FF when write b’10 bit to BCSR4
-- WDEn.clrn = !END_OF_WD_TIMER & !MPC_READ_BCSR_4 & PRST~;
CLEAR_TO_WD_CTRL = LCELL (PRST~);
StartStopWD.clrn = CLEAR_TO_WD_CTRL;
StartStopWD.clk = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”01”));
StartStopWD.s = VCC; StartStopWD.r = VCC; ---- Provide toggling

END_OF_WD_TIMER = WD_TIMER1.dv2 & WD_TIMER1.dv4 & WD_TIMER1.dv8 & WD_TIMER1.dv16 &
       WD_TIMER2.dv2 & WD_TIMER2.dv4 & WD_TIMER2.dv8 & WD_TIMER2.dv16 &
       WD_TIMER3.dv2 & WD_TIMER3.dv4 & WD_TIMER3.dv8 & WD_TIMER3.dv16 &
       WD_TIMER4.dv2 & WD_TIMER4.dv4 & WD_TIMER4.dv8 & WD_TIMER4.dv16 &
       WD_TIMER5.dv2 & WD_TIMER5.dv4 & WD_TIMER5.dv8 & WD_TIMER5.dv16 &
       WD_TIMER6.dv2 & WD_TIMER6.dv4 & WD_TIMER6.dv8 & WD_TIMER6.dv16 &
       WD_TIMER7.dv2 & WD_TIMER7.dv4 & WD_TIMER7.dv8 & WD_TIMER7.dv16 &
       WD_TIMER8.dv2 & WD_TIMER8.dv4;
WD_TIMER1.g = StartStopWD.q; WD_TIMER2.g = StartStopWD.q; WD_TIMER3.g = StartStopWD.q; WD_TIMER4.g =
StartStopWD.q;
WD_TIMER5.g = StartStopWD.q; WD_TIMER6.g = StartStopWD.q; WD_TIMER7.g = StartStopWD.q; WD_TIMER8.g =
StartStopWD.q;

WD_TIMER2.clk = WD_TIMER1.dv16; -- Cascade
WD_TIMER3.clk = WD_TIMER2.dv16; -- Cascade
WD_TIMER4.clk = WD_TIMER3.dv16; -- Cascade
WD_TIMER5.clk = WD_TIMER4.dv16; -- Cascade
WD_TIMER6.clk = WD_TIMER5.dv16; -- Cascade
WD_TIMER7.clk = WD_TIMER6.dv16; -- Cascade
WD_TIMER8.clk = WD_TIMER7.dv16; -- Cascade

HRESET_FEdge.clock = Extclk;
HRESET_FEdge.aclr = HRESET~ OR !R_PORI~;
IF(HRESET_FEdge.q[] == 3) THEN HRESET_FEdge.cnt_en = GND; -- Disable count after term value
ELSE HRESET_FEdge.cnt_en = VCC;
END IF;

RESETS = (HRESET_FEdge.q[] == 1) OR (HRESET_FEdge.q[] == 2) OR
!(R_PORI~ & PRST~);

WD_TIMER1.clr = RESETS; -- Reset first cascade divider
WD_TIMER2.clr = RESETS; -- Reset second cascade divider
WD_TIMER3.clr = RESETS; -- Reset third cascade divider
WD_TIMER4.clr = RESETS; -- Reset forth cascade divider
WD_TIMER5.clr = RESETS; -- Reset third cascade divider
WD_TIMER6.clr = RESETS; -- Reset forth cascade divider
WD_TIMER7.clr = RESETS; -- Reset forth cascade divider
WD_TIMER8.clr = RESETS; -- Reset forth cascade divider

SPARE1 = (HRESET_FEdge.q[] == 1) OR (HRESET_FEdge.q[] == 2);
%
******************************************************************************
%
END;-- End of BCSR module

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Summary of Contents for MSC8101 ADS

Page 1: ... Dragilev Lev SW HW Dept Motorola Semiconductor Israel 1 Shenkar Street Herzlia 46120 Israel TEL 972 9 522 579 email Lev Dragilev motorola com FAX 972 9 9562990 SW HW Dept Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 2: ...MSC8101ADS RevB User s Manual Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 3: ...4 2 SWITCHES 26 4 2 1 Host I F Setting SW1 26 4 2 2 Emulator Enable EE SW2 26 4 2 3 ABORT Switch SW3 27 4 2 4 SOFT RESET SRESET Switch SW4 27 4 2 5 DATA Bus Width Setting SW5 SW6 27 4 2 6 HARD RESET HRESET Switch SW7 28 4 2 7 Power On RESET Switch PRESET SW8 28 4 2 8 Configuration Switch SW9 28 4 2 9 Boot Mode Select SW10 29 4 2 10 Software Options Switch SW11 30 4 3 Jumpers 30 4 3 1 JP1 DLL Disab...

Page 4: ...gisters Programming 34 4 5 1 System Initialization 35 5 1 Reset Reset Configuration 39 5 1 1 Power On Reset 39 5 1 2 Manual Hard Reset 39 5 1 3 Hard Reset Configuration 39 5 1 4 Manual Soft Reset 41 5 1 5 MSC8101 Internal Hard Reset Sources 42 5 2 Local Interrupter 42 5 2 1 ABORT Interrupt 42 5 2 2 ATM UNI Interrupt 42 5 2 3 QFALC Interrupt 42 5 3 Clock Generator 42 5 4 Bus Buffering 43 5 5 Chip S...

Page 5: ...rogramming ISP 90 B 1 4 P4 Host Interface Connector 90 B 1 5 P5 P7 P8 P9 P10 P13 P14 Logic Analyzer Connectors 92 B 1 6 P6 JTAG OnCE Port Connector 92 B 1 7 P12 Ethernet Port Connector 93 B 1 8 P15 P16 SMB Connectors 93 B 1 9 P17 P18 Double RJ45 T1 E1 Line Connectors 93 B 1 10 P19 P21 P24 Stereo Phone Jack Connectors 94 B 1 11 P20 P22 P23 P25 RCA Jack Connectors 94 B 1 12 P26 5V Power Supply Conne...

Page 6: ...VI MSC8101ADS RevB User s Manual MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 7: ...RE 4 1 Switch SW1 HOST Description 26 FIGURE 4 2 Switch SW2 Description 27 FIGURE 4 3 DIP Switch 64 32 Bit Setting 28 FIGURE 4 4 Switch SW9 MODCK Description 29 FIGURE 4 5 Switch SW10 BOOT MODE Description 30 FIGURE 4 6 Switch SW11 S W Option Description 30 FIGURE 4 7 JP4 FLASH Programming Source Selection 31 FIGURE 4 8 JP9 5V CODEC Source Selection 32 FIGURE 5 1 Clock Distribution Scheme 43 FIGUR...

Page 8: ...VIII MSC8101ADS RevB User s Manual MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 9: ...ing 59 TABLE 5 14 Flash Presence Detect 4 1 Encoding 59 TABLE 5 15 BCSR3 Description 60 TABLE 5 16 EXTOOLI 0 3 Assignment 61 TABLE 5 17 External Tool Revision Encoding 61 TABLE 5 18 ADS Revision Encoding 61 TABLE 6 1 MSC8101ADS Memory Map 63 TABLE 7 1 Off Board Application Maximum Current Consumption 66 TABLE A 1 MSC8101ADS Bill Of Material 68 TABLE B1 2 P1 System Expansion Interconnect Signals 77...

Page 10: ...T X MSC8101ADS RevB User s Manual MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 11: ...be used as a demonstration tool i e application s w may be burnedA into its flash memory and ran in exhibitions etc 1 2 Abbreviations List Processor The MSC8101 ADS The MSC8101ADS the subject of this document SDRAM Machine Synchronous Dynamic RAM Machine UPM User Programmable Machine GPCM General Purpose Chip select Machine CPM Communication Processor Module FCC Fast communications controller SCC ...

Page 12: ...Hz Bus Clock Frequency PowerPC 60x bus Total address range Data Bus width Flash memory mounted on SIMM Synchronous DRAM 100MHz soldered non buffered 4 Giga Bytes 32 address lines 256 KBytes External 18 address lines 64 bit without Host Interface HID16 32bit with HID16 8 MByte 32 bits wide expandable to 32 MBytes 16MBytes organized as 2x8Megx32 bit May be reconfiged to 32bits wide with 8MByte expan...

Page 13: ...100 Base T Port on FCC2 with T P I F MII controlled using Level One LXT970 o Four channels T1 E1 on TDMs using Infeneon Quad FALC PEB22554 o 24 bit audio CODEC CS4221 connected to the CPM s TDMA1 channel with gained stereo audio Input Output o Dual RS232 port residing on SCC1 SMC1 o Module disable i e low power mode option for all communication transceivers BCSR controlled enabling use of communic...

Page 14: ... fixed Voltage Regulators for other circuits May be bypassed in case of external power supplying o Software Option Switch provides 8 S W options via BCSR o LED s for power supply module enables timer expired and SW indications Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 15: ... 3V 5V 3 3V 5V 3 3V MC145583 MSC8101 Buffered Exp System Bus JTAG OnCE 14pin To Converter Command 16Mbyte 64bit 1 2 Address Mux for variable Port Size 64 32 332 pin 0 8mm 19x19 matrix 3M Socket 3ns 28 D 32 59 Clock Buffer ClkOut DLLIN TDMA1 CODEC CS4221 From MIC LINE STEREO To STEREO AUDIO AMP 16 4 25MHz Flash Detect HOST I F Host PORT Clock Ext CLK HOST Buffers Additional memory part is optional ...

Page 16: ...trated in FIGURE 2 1 MSC8101 ADS Top Side Part Location diagram on page 17 The board has been factory tested and is shipped with DIP Switch settings as described in the following paragraphs Parameters can be changed for the following conditions The Processor Internal Logic and PLLs Supply Level 1 6V via potentiometer RP2 The Processor I O Supply Voltage 3 3V via potentiometer RP1 be careful since ...

Page 17: ...dware Preparation FIGURE 2 1 MSC8101ADS Top Side Part Location diagram Host SW EE SW 64 32 Select Config SW Boot Mode SW S W Opt Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 18: ...ad from SW9 4 6 or from Host Interface to establish with the multiplication factors of the CPM s and Core s PLLs SW9 is shown in FIGURE 4 4 Switch SW9 MODCK Description on page 29 Some Clock Configuration can see in FIGURE 5 1 on page 43 2 3 3 Setting HReset Configuration Source The HReset Configuration WordA read by the Processor while HRESET is asserted may be taken from three sources 1 Flash Me...

Page 19: ...he ADS by a Command Converter provided by a third party Macraigor Systems FIGURE 3 1 Host System Debug Scheme A 3 2 Host I F Operation In this configuration the MSC8101ADS is using HDI16 I F that provide 16 bit wide full duplex double buffered parallel port to connect directly to the data bus of a host processor The HDI16 supports two classes of interfaces Host processor Microcontroller MCU connec...

Page 20: ...host via one of its other ports e g RS232 port Fast Ethernet port ATM155 port etc Operating in this mode requires an application program to be programmed into the board s Flash memory 5V Power Supply 14 Wire Flat Cable Host Computer Media I F Command Converter 36Wire Flat Cable Host Device To JTAG OnCE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to...

Page 21: ...s to the common of the power supply while Hot line is connected with a single wire NOTE Since hardware applications may be connected to the MSC8101ADS via the expansion connec tors P1 and P2 the additional power consump tion should be taken into consideration when a power supply is connected to the MSC8101ADS 3 5 JTAG OnCE Connector P6 The MSC8101ADS JTAG OnCE connector P6 is a 14 pin two rows hea...

Page 22: ...P4 The MSC8101ADS HOST I F connector P4 is a 36 pin two rows header connector The connection between the MSC8101 ADS and the Host Board is by a 36 line flat cable not shipped with the ADS FIGURE 3 6 P4 Host I F Connector below shows the pin configuration of the connector 1 3 5 7 9 2 4 6 8 10 TDI GND GND TDO N C RESET 11 12 13 14 GND N C KEY NO PIN TMS 3 3V N C TRST TCK Freescale Semiconductor I Fr...

Page 23: ... for 1 1 connection with the serial port of an IBM ATA or compatibles i e via a flat cable The pinout which is not identical P27A supports DTE to DCE connection unlike it the P27B supports Null Modem connection DTE to DTE The difference is shown in FIGURE 3 7 and FIGURE 3 8 A IBM AT is a trademark of International Business Machines Inc 1 3 5 7 9 2 4 6 8 10 HD0 HD2 HD12 HD8 11 12 13 14 15 16 HD14 H...

Page 24: ...work is done by a standard cable having two RJ45 8 jacks on its ends 3 9 Flash Memory SIMM Installation To install a memory SIMM it should be taken out of its package put diagonally in its socket U8 and then raised to a vertical position until the metal lock clips are locked See FIGURE 3 9 Flash Memory SIMM Insertion on page 25 1 TX 2 RX 3 N C 4 CTS 5 DSR 6 GND 7 CD 8 9 N C DTR 1 TX 2 RX 3 N C 4 N...

Page 25: ...nt to align the memory correctly before it is twisted other wise damage might be inflicted to both the memory SIMM and its socket FIGURE 3 9 Flash Memory SIMM Insertion 1 2 SIMM Socket Metal Lock Clip Flash SIMM SIMM Insert Turn Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 26: ... through tri state buffers and sampled by the Processor The SW1 factory set is all ON FIGURE 4 1 Switch SW1 HOST Description 4 2 2 Emulator Enable EE SW2 This switch controls lines EE0 EE7 EED connected to appropriate pins of the Processor When Reset Configuration executed EEs lines involved in one are driven by FPGA In fact they are EE0 EE1 EE4 and EE5 which sampled at the rising edge of PORESET ...

Page 27: ...h SW4 performs Soft Reset to the Processor internal modules maintaining it s configuration clocks chip selects and SDRAMs contents The switch signal is debounced and it is not possible to disable it by software 4 2 5 DATA Bus Width Setting SW5 SW6 Two switches SW5 SW6 are using together for preparing the SDRAM Memory Banks for Host Interface Mode when HDI16 interface is provided over Data Bus line...

Page 28: ...e Processor re acquires the power on reset configuration data from the Flash Altera or Host I F 4 2 8 Configuration Switch SW9 SW9 is a 8 switch DIP Switch This switch is connected over Altera device to MODCK 1 6 lines of the Processor The combination of the switches composing SW9 sets during Power On reset sequence the MODCK 1 6 field for the MSC8101 The switch SW9 7 establishes Configuration Wor...

Page 29: ...oing so BTM s switch position will be ignored See TABLE 5 1 on page 40 for more explanation SW10 is factory set to all ON TABLE 4 1 Available Clock Mode Setting MODCK Clock Mode Clock In MHz CPM MHz PPC Bus MHz SC140 Core MHz 1 2 3 4 5 6 0 0 1 1 1 1 57a 55 137 5 55a a Factory setting 275 0 0 1 0 0 1 9b b Alternative clock mode for 100MHz bus frequency requires clock oscillator 20MHz 20 200 100 300...

Page 30: ...from BCSR When Jumper JP1 is open MSC8101 will be configured without DLL If JP3 will closed the DLL is ON Setting of JP3 is depended on jumper JP2 see JP2 description Default set is JP3 OPEN DLL disable 4 3 2 JP2 Clock Buffer Set Jumper J2 allows to change mode of Zero Delay Buffer JP2 When Jumper JP2 is open ZD buffer operates in normal mode and require DLL disable setting JP1 is open For U44 buf...

Page 31: ...3 NOTE Should be taken into consideration that 12V external power input for Flash SIMM have no protection FIGURE 4 7 JP4 FLASH Programming Source Selection 4 3 5 JP5 JP8 600 Ohm Termination Set for audio measurements Factory set JP5 JP8 are OPEN 4 3 6 JP6 JP7 MIC Enable Set if using external microphone audio source Factory set JP6 JP7 are CLOSE 4 3 7 JP9 5V power supply for CODEC JP9 selects the s...

Page 32: ... on analog ground plane They are meant to assist general measurements and logic analyzer connection Warning When connecting to a GND bridge use only IN SULATED GND clips Otherwise un insulated clips may cause short circuits touching HOT points around them Failure in doing so might result in permanent damage to the MSC8101ADS 4 3 10 Solder Bridges All the solder bridges should be shorted while addi...

Page 33: ... 10 Signaling Indicator 0 LD10 This green indication LED has no dedicated function over the ADS It is meant to provide some visibility for program behavior It is controlled by BCSR0 6 When either of SRESET or Power On Reset is asserted the LED lights as well 4 4 11 RS232 Port 2 ON LD11 When the yellow RS232 Port 2 ON LED is lit it designates that the RS232 transceiver connected to P27B is active a...

Page 34: ...D16 reflects the bit BCSR0 4 T1_234EN 4 4 17 CODEC Enable LD17 When the yellow CODEC LED is lit it indicates that CODEC lines are connected to the CPM TDMA1 port instead of T1 E1 QFALC port 1 When darkened the CODEC device is isolated from the bus by tri state buffers The LD17 reflects the bit BCSR1 1 CODEC_EN 4 4 18 RUN Indicator LD18 When the green RUN LED LD18 is lit it indicates that the MSC81...

Page 35: ...r on the MSC8101ADS is initialized to 50 100 MHz operation I e registers programming is based on 50 100 MHz timing calculation TABLE 4 3 SIU Registers Programming Register Init Value hex Description RMR 0001 Check Stop Reset enabled IMMR 14700000 Internal space begins from 0x1470_0000 SYPCR FFFFFFC3 Software watchdog timer count FFFF Bus monitor timing FF PPC Bus monitor Enabled Local Bus monitor ...

Page 36: ... port size no parity GPCM OR1 FFFF8010 FFFF8020 32 KByte block size all types access 1 w s 32 KByte block size all types access 2 w s BR2 SDRAM 64bit Supported Non buffered PPC 20000041 Base at 20000000 64 bit port size no parity SDRAM machine 1 OR2 MT48LC2M32B2T6 8x2 by Micron FF003080 16MByte block size 4 banks per device row starts at A8 11 row lines internal bank interleaving allowed BR2b SDRA...

Page 37: ...t data out to precharge 2 1 clock write recovery time Internal address muxing normal timing 3 2 clocks CAS latency SDRAM 32bit Non buffered PPC with Host support C28737A3 C2432552 Page interleaving Refresh enabled normal operation address muxing mode 1 A 13 15 on BNKSEL 0 2 A9 on PSDA10 8 4 clocks refresh recovery 3 2 clocks precharge to activate delay 3 2 clocks activate to read write delay 8 bea...

Page 38: ... RAM address begins at 18H Exception Access 1001543c RAM address begins at 0x3c Normal Operation 00015400 Execute at 0x0 a Table values in parentheses reflect the lower frequency bus b With Host Enable c If additional SDRAM device U38SP will be assembled on the ADS special requirement TABLE 4 4 Memory Controller Initialization for 100 50 a MHz Reg Device Type Bus Init Value hex Description Freesca...

Page 39: ...ion Word on page 40 MODCKs bits are sampled at hard reset configuration whenever hard reset sequence is entered they are influential only once after power on reset If a hard reset sequence is entered later on these bits although sampled are don t care 5 1 2 Manual Hard Reset To allow run time Hard reset when the Command Converter is disconnected from the MSC8101ADS and to support resident debugger...

Page 40: ...ion Reset mode The Host device which must not be MSC8101 write two 16 bit words to program 32 bit Reset Conf Word See a table below including the several boot mode TABLE 5 1 Summary Reset Configuration Schemes For Debug and Boot Mode setting will be used separate DIP switch array EEs and EED pins are controlled from another DIP switch and may be read out from status register of the BCSR3 The follo...

Page 41: ...t address 0xF0000000 BMS 16 0 Non functional cleared bit 10 02 BBD 17 0 Bus busy pins set ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB Reserved 18 21 0000 Must be cleared TCPC 22 23 10 Transfer code pins are configured following way after PONRESET MODCK1 BNKSEL 0 TC 0 as BKSEL0 MODCK2 BNKSEL 1 TC 1 as BKSEL1 MODCK3 BNKSEL 2 TC 2 as BKSEL2 BC1PC 24 25 00 Buffer control 1 pin configuration BCTL1 DBG_DIS ...

Page 42: ...port ATM UNI User Network I F event report by means of interrupt the interrupt output of the UNI INTB is connected to IRQ6 line of the MSC8101 Since INTB of the UNI is an open drain output it is possible to connect additional off board inter rupt requesters on the same IRQ6 provided that they drive IRQ6 with open drain gate as well 5 2 3 QFALC Interrupt Interrupt of T1 E1 Frame are served by IRQ7 ...

Page 43: ...B buffered board address or during Hard Reset configurationC That way data conflicts are avoided in case an unbuffered memory read or off board memory is read provided that it is not mapped to an address valid on board It is the users responsibility to avoid such errors 5 5 Chip Select Generator The memory controller of the MSC8101 is used as a chip select generator to access on board and off boar...

Page 44: ...In this case we can use one from two SDRAM chip therewith the second chip will be disable with BCSR s control bit memory space will be decreased by half The system bus of the MSC8101 is very fast and run up to 100MHz therefore any type of logic for address mux puts large timing penalty and impossible The mux is done by jumper s array See FIGURE 5 2 SDRAM Connection Scheme on page 45 The SDRAM s ti...

Page 45: ...below TABLE 5 4 100 MHz SDRAM Mode Register Programming SDRAM Address Linea a Actually SDRAM s A0 is connected to MSC8101 A29 A28 address line 32 64 bit width mode SDRAM Mode Reg Field Value Meaning A10 Reserved 0 Should program zero A9 WB 0 Read Write Burst Access A8 A7 Operation Mode 00 Standard Operation A6 A4 CAS Latency 3 2b CAS Latency A3 Burst Type 0 Sequential A2 A0 LSB Burst Length 010 01...

Page 46: ...e Flash SIMM Presence Detect lines see TABLE 5 13 Flash Presence Detect 7 5 Encoding on page 59 the debugger can establish via register OR0 the correct number of wait states needed to access the Flash SIMM considering default system clock frequency The control over the Flash is done with the GPCM and a dedicated CS0 region which controls the whole bank During hard reset initializationB the debugge...

Page 47: ... is given to modules that require 5V for programming The 5V voltage for programming is taken from the main board voltage supply or 12V from external power supply in protection mode BD 0 31 BA 9 29 D 31 0 A 22 0 FPD1 FPD2 FPD3 FPD4 PD1 PD2 PD3 PD4 FPD5 PD5 FPD6 FPD7 PD6 PD7 FLASH SIMM BCSR BWE0 BWE1 BWE2 BWE3 BPOE FCS0 FCS1 FCS2 FCS3 WE0 WE1 WE2 WE3 OE CS0 CS1 CS2 CS3 FCSb BA 7 8 ADR Ext Flash Type...

Page 48: ...tors residing on the edge of the board The communication ports interfaces provided on the MSC8101ADS are listed below 1 155 Mbps ATM UNI on FCC1 with Optical I f connected via UTOPIA I F 2 100 10 Base T Port on FCC2 with T P I F MII controlled 3 Four T1 E1 ch on TDMA1 B2 C2 D2 ports 4 Audio CODEC on TDMA1A 5 Dual RS232 port residing on SCC1 SMC1 Not all peripherals are available at once For unders...

Page 49: ... PA27 MIIRXDV ATM8 RxSOC PA28 MIITXEN ATM8 RxEnb PA29 MIITXER ATM8 TxSOC PA30 MIICRS ATM8 TxClav PA31 MIICOL ATM8 TxEnb PB18 MIIRXD3 PB19 MIIRXD2 PB20 TDMD2 L1RSYNC MIIRXD1 D PB21 TDMD2 L1TSYNC MIIRXD0 PB22 TDMD2 L1RXD MIITXD0 D PB23 TDMD2 L1TXD MIITXD1 D PB24 TDMC2 L1RSYNC MIITXD2 D PB25 TDMC2 L1TSYNC MIITXD3 PB26 TDMC2 L1RXD MIICRS D PB27 TDMC2 L1TXD MIICOL D PB28 TDMB2 L1TSYNC MIIRXER PB29 TDMB...

Page 50: ... hard configured The ATM SAR is connected to the physical medium by an optical I F Use is done with HP s HFBR 5205 optical I F which operates at 1300 nm with upto 2 Km transmission range 5 8 2 100 10 Base T Port A Fast Ethernet port with T P 100 Base TX I F is provided on the MSC8101ADS This port is also support 10 Mbps ethernet 10 Base T via the same transceiver the LXT970 by Level One The LXT970...

Page 51: ...etting FIGURE 5 4 MSC8101 to CODEC connection 5 8 3 1 CS4221 Programming After power up the CODEC device needs to be initialized over SPI port of the CPM The pulldown resistor on SDOUT pin causes the part operates in Clock Master Mode To communicate with the CS4221 the chip address field must be 001000 The control register contains eight bytes which are selected by memory address pointer of three ...

Page 52: ...tes RS232 levels internally using a single 3 3V supply and has shutdown mode during which receive buffers are tri stated When the RS232EN1 or RS232EN2 bits in BCSR1 6 7 is asserted low the corresponding transceiver is enabled When negated the corresponding trans ceiver is enter standby mode within which the receiver outputs are tri stated enabling use of the corresponding port s pins off board via...

Page 53: ... HRRQ HACK direction are controlled by corresponding bits of the BCSR0 1 2 See FIGURE 5 6 Host Interface Diagram below Buffer transceivers are 5V compliant Host Port is also available via two row header 36 pins FIGURE 5 6 Host Interface Diagram The MSC8101 CPM ports are poorer than the MPC8260 CPM therefore Host I F bus may be driven outside through CPM Expansion Connector in place of unusable lin...

Page 54: ...isters BCSR0 to BCSR7 Since the minimum block size for a CS region is 32KBytes and only A 27 29 lines are decoded by the BCSR for register selection BCSR0 BCSR7 are duplicated many times inside that region See also TABLE 1 1 MSC8101ADS Spec ifications on page 12 The following functions are controlled monitored by the BCSR 1 PPC Data Bus width 64 32 bits 2 CODEC Enable Disable 3 QFALC Con Pin No Si...

Page 55: ...ason to achieve maximum SW compatibility with Voyager ADS the usable control status bits will be populated at the corresponding addresses 5 11 1 BCSR0 Board Control Status Register 0 The BCSR0 serves as a control register on the ADS Although it resides only over D 0 7 lines of the PPC data bus it is accessed as a word at offset 0 from BCSR base address It may be read or written at any time BCSR0 g...

Page 56: ...by HRESET signal of the MSC8101 1 R W 6 SIGNAL_LAMP_0 Signal Lamp 0 When this signal is active low a dedicated Green LED illuminates When in active this LED is darkened This LED may be used for S W signalling to user 1 R W 7 SIGNAL_LAMP_1 Signal Lamp 1 When this signal is active low a dedicated Red LED illuminates When in active this LED is darkened This LED may be used for S W signalling to user ...

Page 57: ... the LXT970 is driven low with this application the negation of this signal causes all the H W configuration bits to be sampled for initial values and device control is moved to the MDIO channel which is the control path of the MII port 1 R W 6 RS232EN_1 RS232 port 1 Enable When asserted low the RS232 transceiver for port 1 upper is enabled When negated the RS232 transceiver for port 1 is in stand...

Page 58: ...ield may contains the revision code of an external tool connected to the ADS The various combinations of this field will be described per each tool user s manual These signals are available at the System Expansion connector R 12 15 EXTTOLI 0 3 External Tools Identification These lines which are available at the CPM expansion connectors are intended to serve as tools identifier On board S W may che...

Page 59: ...ABLE 5 13 Flash Presence Detect 7 5 Encoding on page 59 R 28 31 FLASH_PD 4 1 Flash Presence Detect 4 1 These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH_PD 4 1 see TABLE 5 14 Flash Presence Detect 4 1 Encoding on page 59 R a There is additional bit to this field See bit 24 in the same tab...

Page 60: ...ding an option to manually program debugging 0 R 1 EE1 Emulation Enable 1 Same as EE0 0 R 2 EE2 Emulation Enable 2 Same as EE0 0 R 3 EE3 Emulation Enable 3 Same as EE0 0 R 4 EE4 Emulation Enable 4 Same as EE0 0 R 5 EE5 Emulation Enable 5 Same as EE0 0 R 6 EED Event Detection Same as EE0 0 R 7 Reserved Un Implemented Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This...

Page 61: ... F Tool F External Tool is Not Present TABLE 5 17 External Tool Revision Encoding TOOLREV 0 3 hex External Tool Revision 0 ENGINEERING 1 PILOT 2 A 3 B 4 F Reserved TABLE 5 18 ADS Revision Encoding Revision Number 0 3 Hex ADS Revision 0 ENG Engineering 1 PILOT 2 A 3 B 4 F Reserved Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 62: ...e user After Hard Reset is performed by the debug station the debugger checks for existance size delay and type of the FLASH memory SIMM mounted on board and initializes the memory controller accordingly The SDRAM and the FLASH memory respond to all types of memory access i e problem supervisory program data Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product...

Page 63: ...FF DSP Peripherals CS11 64 01F10000 01FFFFFF Empty Space 02000000 0207FFFF Internal SRAM CS10 64 02080000 144FFFFF Empty Space 14500000 14507FFF BCSR 0 3 b 32 14500000 14507FF3 BCSR0 14500004 14507FF7 BCSR1 14500008 14507FFB BCSR2 1450000C 14507FFF BCSR3 14508000 145FFFFF Empty Space 14600000 14607FFFc ATM UNI Proc Control PMC5350 8 14608000 1460FFFFc T1 E1 Framer QFALC 8 14610000 146FFFFF Empty S...

Page 64: ...at memory locations 14700000 14700010 14700020 while BCSR1 appears at 14700004 14700014 14700024 and so on c The internal space of the ATM UNI control port is 256 bytes however the minimal block size that may be controlled by a CS region is 32KBytes The same reason is for another peripherals d Initially at hF0000000 hF000FFFF set by hard reset configuration e Refer to the MSC8101 spec for complete...

Page 65: ...pment two of the power buses are connected to the ex pansion connectors so that external logic may be powered directly from the board The maximum current allowed to be drawn from the board on each bus is shown in TABLE 7 1 Off Board Appli 3 3 10 V 0 9 2 2 V 5V MSC8101 QVCC VCCSYN ADS Logic Peripherals NVCC Expansion Con 1V5CR VCCSYN1 5V0 3V3 P26 JS3 JS2 3V3IO 1V5 JS5 JS4 JS1 QHCC F1 4A JP3 CODEC 5...

Page 66: ...tion logic blows the fuse while limiting the mo mentary effects on board 7 1 2 3 3V Bus The MSC8101 the SDRAMs the address and data buffers are powered by the 3 3 bus which is produced from the 5V bus using a low voltage drop linear voltage regulator LM1085S the which is capable of driving upto 4A facilitating operation of external logic as well 7 1 3 1 5V Bus The MSC8101 s internal logic and the ...

Page 67: ...MOTOROLA MSC8101ADS RevB User s Manual A 67 APPENDIX A MSC8101 Bill of Material Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 68: ...3 C205 C206 C207 C208 Capacitor 0 1µF 16V 10 SMD 0603 Ceramic AVX 0603YC104KAT2A C5 C71 C107 C125 C139 C141 Capacitor 68µF 20V 20 SMD Size D Tantalum AVX TAJD686K020R C10 C11 C184 C196 Capacitor 47µF 16V 10 SMD Size D Tantalum AVX TAJD476K016 C12 C13 Capacitor 2200pF 50V X7R 50V 10 SMD Size 1206 Ceramic AVX AV12065C222KATJ C16 C17 C18 C19 Capacitor 47µF 25V 10 Electrolit JAMICON TKR470M1ED11 C25 C...

Page 69: ... 1206 KINGBRIGHT KPT 3216YD LD5 LD9 Led Red SMD Size 1206 KINGBRIGHT KPT 3216ID LD2 LD3 LD6 LD7 LD8 LD10 LD18 LD20 LD21 LD22 Led Green SMD Size 1206 KINGBRIGHT KPT 3216SGD JG1 JG2 JG3 JG4 JG5 JG6 Gnd Bridge Gold Plated 5mm PRECIDIP PD999 11 11210 JS1 JS2 JS3 JS4 JS5 Gnd Bridge Gold Plated 5mm PRECIDIP PD999 11 11210 JP4 JP9 Jumper Header 3 Pole with Fabricated Jumper MOLEX 87156 0303 JP1 JP2 JP3 J...

Page 70: ...18 Resistor 10 KΩ 0 1 SMD 1206 1 4W RCD BLU1206 10K 0 1 R21 R23 R196 Resistor 47 KΩ 1 SMD 1206 1 4W RODERSTEIN D25 047KFCS R24 R25 R212 R213 R214 R217 R223 R224 Resistor 20 KΩ 1 SMD 1206 1 4W RODERSTEIN D25 020KFCS R26 R27 R204 R205 R216 R219 Resistor 150 Ω 5 SMD 1206 1 4W RODERSTEIN D25 150RJCS R28 R51 R155 R156 R164 R165 R176 R177 R182 R183 Resistor 10Ω 1 SMD 1206 SMD 1 4W AVX CR32 10ROF T R29 R...

Page 71: ...SMD 0603 0 1W DRALORIK D11 133RFCS R99 R100 R107 Resistor 82 5 Ω 1 SMD 0603 0 1W DRALORIK D11 82R5FCS R104 R128 Resistor 1 5 Ω 1 SMD 1206 1 4W RODERSTEIN D25 01R5FCS R109 Resistor 43 2Ω 1 SMD 0603 0 1W DRALORIK D11 43R2FCS R118 R122 Resistor 270 Ω 1 SMD 1206 1 4W DRALORIK D25 270RFCS R120 Resistor 63 4 Ω 1 SMD 0603 0 1W DRALORIK D11 63R4FCS R144 R151 Resistor 20 Ω 1 SMD 0603 0 1W DRALORIK D11 020R...

Page 72: ...11 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN31 RN32 RN33 RN36 RN37 RN39 RN40 RN41 RN43 RN58 RN62 RN63 RN65 Resistor Network 10 KΩ 5 8 resistors 10 pin Common Bus ROHM RS8A 1002J RP1 Trimmer Potentiometer 1K single turn BOURNS 3362P 1 102 RP2 Potentiometer 1K multi turn BOURNS 3296Y 1 102 SW1 SW10 SW11 Dip Switch 4 X SPST SMD GRAYHILL 90HBW04SR SW2 SW9 Dip Switch 8 X SPST SMD G...

Page 73: ... 20 pin TSSOP pkg CASE 948E 02 ON SEMICONDUCTOR MC74LCX541DT U14 Saturn User Network I F S UNI for 155 52 51 84 Mbps 128 pin PQFP PMC Sierra Inc PM5350 RC U15 Fiber Optic I F Module 1300 nm wavelength 2 Km Range HP HFBR 5205 U16 U37 U38 Low Voltage CMOS 5V Tolerant 16 bit buffer with OEs 48 pin Plastic TSSOP Case 1201 01 MOTOROLA MC74LCX16244DT U17 MCS8101 MOTOROLA PC8101FC300A Socket 0 80mm Ball ...

Page 74: ...er 8 outputs 3 3V IDT IDT2309 1HPG U46 U47 Low Voltage CMOS 5V Tolerant 16 bit Transceiver with Bus Hold 48 pin Plastic TSSOP PHILIPS 74ALVT16245DL U49 Dual TMOS Power N Chanel MOSFET 4A 20V SO 8 ON SEMICONDUCTOR MMDF4N01HD U50 Low Voltage Rail to Rail OpAmp SO 8 pkg ON SEMICONDUCTOR MC33202D U51 High Precision Voltage Detector Range 1 0V 2 O D output SC 82AB pkg SEIKO S 80810ANNP Y1 Crystal reson...

Page 75: ...MOTOROLA MSC8101ADS RevB User s Manual A 75 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 76: ...MOTOROLA MSC8101ADS RevB User s Manual B 75 APPENDIX B Support Information Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 77: ...ax Connectors 9 P17 P18 Double RJ45 for T1 E1 port 10 P19 P21 P24 Stereo Phone Jack 11 P20 P22 P23 P25 RCA Jack 12 P26 5V Power Supply 13 P27A B RS232 port 1 2 B 1 1 MSC8101ADS s P1 System Expansion Connector P1 is a 128 pin 900 DIN 41612 connector which provide a minimal system I F required to inter face various types of communication transceivers data path of which passes through MSC8101 s This ...

Page 78: ...7 EXPA22 A8 EXPA23 A9 EXPA24 A10 EXPA25 A11 EXPA26 A12 EXPA27 A13 EXPA28 A14 EXPA29 A15 EXPA30 A16 EXPA31 A17 N C Not connected A18 A19 EXPDVALb I O T S Expansion 60x bus Data Valid signal A20 3V3 P 3 3V Power Out These lines are connected to the main 3 3V plane of the MSC8101ADS this to provide 3 3V power where necessary for external tool connected The amount of current allowed to be drawn from t...

Page 79: ...up on the ADS by 10 KΩ resistor s network See also TABLE 5 12 BCSR2 Description on page 58 B13 TOOLREV1 B14 TOOLREV2 B15 TOOLREV3 B16 EXTOLI0 I P U External Tool Identification 0a 3 This lines should be driven by an external tool with the Tool Identification Code to be read via BCSR2 of the ADS These lines are pulled up on the ADS by 10 KΩ resistor s network See also TABLE 5 12 BCSR2 Description o...

Page 80: ... CS7 line reserved for an external tool C6 GND P Digital Ground Connected to main GND plane of the ADS C7 ATMENb O ATM Port Enable This line enables the ATM port UNI s output lines towards the MSC8101 An external tool using the same pins as does the ATM port should consult this signal before driving the same lines Failure to do so might result in permanent damage to the PM5350 ATM UNI C8 ATMRSTb O...

Page 81: ...rted Otherwise they are tristated The direction of these lines is determined by buffered BCTL0 in function of R W C15 EXPD1 C16 EXPD2 C17 EXPD3 C18 EXPD4 C19 EXPD5 C20 EXPD6 C21 EXPD7 C22 EXPD8 C23 EXPD9 C24 EXPD10 C25 EXPD11 C26 EXPD12 C27 EXPD13 C28 EXPD14 C29 EXPD15 C30 IRQ4b I P U Interrupt Request 4 Connected to MSC8101 s DP4 IRQ4b DREQ3 signal Pulled up on the ADS with a 10 KΩ resistor This ...

Page 82: ...l over memory device if necessary These are output only signals and therefore do not support H W controlled UPM waits GPL4 as such UPWAIT D8 EXPGL1b D9 EXPGL2b D10 EXPGL3b D11 EXPGL4b D12 EXPGL5b D13 GND P Digital Ground Connected to main GND plane of the ADS D14 V3 3 P 3 3V Power Out These lines are connected to the main 3 3V plane of the MSC8101ADS this to provide 3 3V power where necessary for ...

Page 83: ...T S When RS232 port 1 is enabled this signal is the receive data line for SCC1 port When this port is disabled this signal is tristated and may be used to any available alternate function for PD31 A2 SCC1RXD PD30 I O T S When RS232 port 1 is enabled this signal is the transmit data line for SCC1 port When this port is disabled this signal may be used to any available alternate function for PD30 A3...

Page 84: ... strobe host bus this pin is the data strobe Schmitt trigger input HDS When the HDI16 is programmed to interface to a double data strobe host bus this pin is the write data strobe Schmitt trigger input HWR Present as well as at P4 connector A25 PD7 MSC8101 s Port D7 Parallel I O line May be used to any of its available functions A26 A28 N C Not connected A29 ATRCKDIS I ATM Receive Clock Out Disabl...

Page 85: ...f Cell H When this signal is asserted High while the ATM port is enabled it indicates that the 1 st octet of data for the received cell is available at the PM5350 s ATMRXD 7 0 lines This line is updated over the rising edge of ATMRFCLK When the ATM port is disabled this line is tristated and may be used for any available function for PA27 B6 ATMRCA PA26 I O T S ATM Receive Cell Available H When th...

Page 86: ...d this line may be used for any available function of PA8 Port A B27 PA5 I O T S MSC8101 s Port A 5 2 Parallel I O lines May be used to any of their available functions B28 PA4 B29 PA3 B30 PA2 B31 HD14 I O T S Host Interface Bidirectional Data Port D14 and D15 Present as well as at P4 connector B32 HD15 C1 FETHTXER PB31 I O T S Fast Ethernetd Transmit Error H When the Ethernet port is enabled this...

Page 87: ...r Sense H When this signal is asserted High while the Ethernet port is enabled and the LXT970 is in half duplex mode it indicates that either the transmit or receive media are non idle When the LXT970 is in either full duplex or repeater operation it indicates that the receive medium is non idle When the Ethernet port is disabled this line may be used for any available function of PB26 C7 FETHTXD3...

Page 88: ...nctions D3 FETHRXCK PC29 I O T S Fast Ethernet Receive Clock When the Ethernet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is extracted from the received data and driven to the MSC8101 to qualify incoming receive data When the Ethernet port is disabled this line is tristated and may be used for any available function of PC29 D4 FETHTXCK PC28 I O T S Fast Ethernet Transmit Cl...

Page 89: ...rnal DMA tool When the DMA port is disabled this line may be used for any available function of PC23 D10 DREQ1b PC22 I O T S DMA channel 1 data request acknowledge This signal is asserted by the DMA indicating that the DMA has sampled the peripheral request Using for external DMA tool When the DMA port is disabled this line may be used for any available function of PC22 D11 N C Not connected D12 D...

Page 90: ...5 9 BCSR0 Description on page 55 D25 PC7 I O T S MSC8101 s Port C 7 6 Parallel I O lines May be used to any of their available functions D26 PC6 D27 SMCTX1 PC5 I O T S When RS232 port 2 is enabled this signal is the transmit data line for SMC1 port When this port is disabled this signal may be used to any available alternate function for PC5 D28 SMCRX1 PC4 I O T S When RS232 port 2 is enabled this...

Page 91: ...Test port Clock This clock shifts in out data to from the programmable logic JTAG chain 2 GND P Digital GND Main GND plane 3 TDO O ISP Transmit Data Output This the prog logic s JTAG serial data output driven by Falling edge of TCK 4 VCC P Connect to 3 3V power supply bus for feeding an external programmer logic 5 TMS I ISP Test Mode Select This signal qualified with TCK changes the state of the p...

Page 92: ...1 3 P2 CPM Expansion Interconnect Signals above 27 HACK I O T S Host Acknowledge or Receive Host Request Output For further explanation see P2 D24 in TABLE B1 3 P2 CPM Expansion Interconnect Signals above 28 HREQ O T S Host Request or Transmit Host Request Output For further explanation see P2 D21 in TABLE B1 3 P2 CPM Expansion Interconnect Signals above 29 HRW I Host Read Write or Host Read Input...

Page 93: ...nals above 33 3V3 P 3 3V Power Out These lines are connected to the main 3 3V plane of the MSC8101ADS 34 N C Not connected 35 GND P Digital GND Main GND plane 36 TABLE B1 6 P6 JTAG ONCE Connector Interconnect Signals Pin No Signal Name Attribute Description 1 TDI I Transmit Data In This is the JTAG serial data input of the ADS sampled on the rising edge of TCK 2 GND P Digital GND Main GND plane 3 ...

Page 94: ... ADS logic 10 TMS I Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machines This line is pulled up internally by the MSC8101 11 VDD P Connect to 3 3V power supply bus May be used for Command Convertor power 12 N C Not Connected 13 14 TRSTb I Test port Reset When this signal is active Low it resets the JTAG logic of both the MSC8101 This line i...

Page 95: ...ir Transmit Data 1 ch negative output from the MSC8101ADS A6 GND Digital Ground plane A7 N C Not Connected A8 B1 RX2 Twisted Pair Receive Data 2 ch positive input from the MSC8101ADS B2 RX2 Twisted Pair Transmit Data 2 ch positive input from the MSC8101ADS B3 GND Digital Ground plane B4 TX2 Twisted Pair Transmit Data 2 ch positive output from the MSC8101ADS B5 TX2 Twisted Pair Transmit Data 2 ch n...

Page 96: ...Data output from the MSC8101ADS A3 RXD Receive Data input to the MSC8101ADS A4 DTR Data Terminal Ready input to the MSC8101ADS A5 GND Ground signal of the MSC8101ADS A6 DSR Data Set Ready output from the MSC8101ADS shorted to pin 1 A7 N C Not connected A8 CTS Clear To Send output from the MSC8101ADS A9 N C Not connected TABLE B1 11 P27B Interconnect Signals Pin No Signal Name Description B1 N C No...

Page 97: ...B 96 MSC8101ADS RevB User s Manual MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 98: ...MOTOROLA MSC8101ADS RevB User s Manual C 97 APPENDIX C Program Information Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 99: ...gic device Altera CPLD serving control and stasus function on the ADS It implemented an U2 EPM7128ATC144 7 The design is done in AHDL program format and is listed below Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 100: ...SV1_0_ACTIVE 1 CONSTANT RSV1_0_NACTIVE 0 CONSTANT RSV1_1_ACTIVE 1 CONSTANT RSV1_1_NACTIVE 0 CONSTANT ATM_ENABLED 0 CONSTANT ATM_DISABLED 1 CONSTANT ATM_RST_ON 0 CONSTANT ATM_RST_OFF 1 CONSTANT FETHI_ENABLED 0 CONSTANT FETHI_DISABLED 1 CONSTANT FETH_RST_ON 0 CONSTANT FETH_RST_OFF 1 CONSTANT RS232_1_ENABLED 0 CONSTANT RS232_1_DISABLED 1 CONSTANT RS232_2_ENABLED 0 CONSTANT RS232_2_DISABLED 1 BCSR3 CO...

Page 101: ...IS When Start Poreset State Rst_True GND if PushBtn 1 then RstEnsureMachine Start else RstEnsureMachine Rst1 PushButton Pressed end if When Rst1 First check of PushButton Succeded Rst_True GND if PushBtn 1 then RstEnsureMachine Start else RstEnsureMachine Rst2 end if When Rst2 Second check of PushButton Succeded Rst_True GND if PushBtn 1 then RstEnsureMachine Start else RstEnsureMachine Rst3 end i...

Page 102: ... Reset_Ensure INCLUDE bcsr INCLUDE lpm_counter INCLUDE lpm_shiftreg INCLUDE freqdiv OPTIONS BIT0 ANY allows a b and b a alignment BCSR0 Power On Default Assignments CONSTANT HOSTCSP_PON_DEFAULT HOSTCSP_NEGATIVE CONSTANT HOSTRQAC_PON_DEFAULT HOSTRQAC_DEF CONSTANT HOSTTRI_PON_DEFAULT HOSTTRI_DEF CONSTANT T1_1EN_PON_DEFAULT T1_1EN_DISABLED CONSTANT T1_234EN_PON_DEFAULT T1_234EN_DISABLED CONSTANT FrmR...

Page 103: ...e BCSR0 CONSTANT SIZE1 7 MSB of the BCSR1 CONSTANT SIZE3 7 MSB of the BCSR3 CONSTANT SIZE4 7 MSB of the BCSR4 CONSTANT SIZE5 7 MSB of the BCSR5 CONSTANT SIZE6 2 MSB of the BCSR6 Hard Reset Configuration Word CONSTANT EARB_DEFAULT 0 CONSTANT EXMC_DEFAULT 0 CONSTANT IRQ7INT _DEFAULT 1 CONSTANT EBM_DEFAULT 0 CONSTANT BPS_DEFAULT0 1 CONSTANT BPS_DEFAULT1 1 CONSTANT SCDIS_DEFAULT 0 CONSTANT ISPS_DEFAUL...

Page 104: ... MODCK_H 1 3 MODCK dip switch bits 4 through 6 INPUT MODCK_BNK 0 2 SDRAM BANK SELECT NMI OUTPUT HDSP HOST RD WR polarity H8BIT HOST SPARE HOSTPD HOST PRESENCE DETECT HOSTCFG INPUT HOSTCFG signal from DIP SW Active LOW HDIMDEN HOST SW ENABLE RSTCNF OUTPUT RESET CONFIG to 8101 SRESET Soft Reset O D HRESET BIDIR Hard Reset O D HDILED HOST LED O D BPOE FLASH OE Option WE0 WE0 Option PSDVAL PSDVAL Opti...

Page 105: ...able T234_EN_OUT T1 Channels 2 3 4 enable BIDIR FrmRst_Out Framer Reset SIG_LAMP0_OUT AUX Output 0 for USER Software Green LED Indicator SIG_LAMP1_OUT AUX Output 1 for USER Software Red LED Indicator OUTPUT BCSR1 OUTPUT CODECEN_OUT Enable CODEC BIDIR ATM_EN_OUT ATM Enable ATM_RST_OUT Reset to ATM This line is also HRESET driven FETHIEN_OUT Fast Ethernet Port Initial Enable FETH_RST_OUT Fast Ethern...

Page 106: ... disables the debouncing of all 3 reset push buttons in case of 3 msec bouncing time Equal count is 2 19 ResetEnsure lpm_counter WITH LPM_WIDTH 19 LPM_DIRECTION UP PRST_Ensure lpm_counter WITH LPM_WIDTH 5 LPM_DIRECTION UP Provide Altera safe Power on Reset to initiate BCSR4 register EE0_HOLD lpm_counter WITH LPM_WIDTH 12 LPM_DIRECTION UP Hold EE0 in high up to X clocks after HRESET becomes disasse...

Page 107: ... Misc Node WritetoBcsr PRST_Ensure_END End of Altera PRST count NODE BCSRs Bits Description BCSR0 HOSTCSP BCSR0 Bit 0 Host CS Polarity HOSTRQAC BCSR0 Bit 1 Host Request or Acknowledge Select HOSTTRI BCSR0 Bit 2 Host Request or Acknowledge Enable T1_1EN BCSR0 BIT 3 T1 port 1 enable T1_234EN BCSR0 Bit 4 T1 ports 1 2 3 are enable FrmRst BCSR0 Bit 5 Framer Reset SIGNAL_LAMP_0 BCSR0 Bit 6 LED0 illumina...

Page 108: ...amming MPC_WRITE_BCSR_0 MPC_WRITE_BCSR_1 MPC_WRITE_BCSR_4 MPC_WRITE_BCSR_5 MPC_WRITE_BCSR_6 MPC_READ_BCSR_0 MPC_READ_BCSR_1 MPC_READ_BCSR_2 MPC_READ_BCSR_3 MPC_READ_BCSR_4 MPC_READ_BCSR_5 MPC_READ_BCSR_6 BCSR0_PON_DEF 0 SIZE0 Power ON default value of BCSR1 BCSR1_PON_DEF 0 SIZE1 Power ON default value of BCSR2 BCSR3_PON_DEF 0 SIZE3 Power ON default value of BCSR3 BCSR0_PON_CONST 0 SIZE0 BCSR1_PON_...

Page 109: ...IZE1 q EE0_node EE1_node EE2_node EE3_node EE4_node EE5_node EED_node RSV3_7 EE 0 5 EED GND MODCK4r MODCK5r MODCK6r MODCK1r MODCK2r MODCK3r Bcsr4 2 SIZE4 q Power On Defaults Value Generation BCSR0 BCSR0_PON_CONST 0 5 HOSTCSP_PON_DEFAULT HOSTRQAC_PON_DEFAULT HOSTTRI_PON_DEFAULT T1_1EN_PON_DEFAULT T1_234EN_PON_DEFAULT FrmRst_PON_DEFAULT BCSR0_PON_CONST 6 SIZE0 SIG_LMP0_PON_DEFAULT SIG_LMP1_PON_DEFAU...

Page 110: ...F END GENERATE FOR i IN 0 to SIZE3 GENERATE IF BCSR3_PON_CONST i THEN BCSR3_PON_DEF i VCC ELSE BCSR3_PON_DEF i GND END IF END GENERATE END Generation Clock Assignments Bcsr0 clk GLOBAL clock Bcsr1 clk GLOBAL clock Bcsr4 clk ExtClk Bcsr5 clk ExtClk Bcsr6 clk ExtClk DivEn clk ExtClk SyncHardReset clk ExtClk DSyncHardReset clk ExtClk PRST_Ensure clock ExtClk EE0_HOLD clock ExtClk EE45_HOLD clock ExtC...

Page 111: ...o N clocks TRI DBGEN GND RESETi or SRESET EE1 TRI HOSTCFG RESETi Assign HPE Via EE1 net EE2 TRI GND GND EE3 TRI GND GND EE4 TRI BTM0 VCC RESETi or SRESET or EE45_HOLD_END EE5 TRI BTM1 VCC RESETi or SRESET or EE45_HOLD_END EED TRI GND GND RSTCNF TRI HOSTCFG RESETi RSTCNF IS ENABLED depends on HOSTCFG on R_PORI rise ver 2 0 REGULAR_POWER_ON_RESET R_PORI REGULAR_PON_RESET_ACTIVE SyncHardReset d HRESE...

Page 112: ...0x14 Bcsr6Write WritetoBcsr A27 A28 A29 Address ending 0x18 MPC_WRITE_BCSR_0 Bcsr0Write BCSR_WRITE_ACTIVE MPC_WRITE_BCSR_1 Bcsr1Write BCSR_WRITE_ACTIVE MPC_WRITE_BCSR_4 Bcsr4Write BCSR_WRITE_ACTIVE MPC_WRITE_BCSR_5 Bcsr5Write BCSR_WRITE_ACTIVE MPC_WRITE_BCSR_6 Bcsr6Write BCSR_WRITE_ACTIVE MPC_READ_BCSR_0 CS1 W_R A27 A28 A29 Address ending 0x0 MPC_READ_BCSR_1 CS1 W_R A27 A28 A29 Address ending 0x40...

Page 113: ...default values from DIP Switch ELSIF MPC_WRITE_BCSR_4 THEN Bcsr4 2 SIZE4 d D 2 SIZE4 Write to the Register ELSE Bcsr4 2 SIZE4 d Bcsr4 2 SIZE4 q END IF BCSR5 Service Register 2 Write Operation IF RESETi THEN Bcsr5 d 0 Load default values when Reset ELSIF MPC_WRITE_BCSR_5 THEN Bcsr5 0 SIZE5 d D 0 SIZE5 Read the Data Bus ELSE Bcsr5 d Bcsr5 q END IF BCSR6 Service Register 3 Write Operation IF RESETi T...

Page 114: ...EAD F_Cs0 HARD_RESET_ACTIVE CONF_ADD 0 FROM_FLASH_CNFG_WORD FROM_HOST_CNFG_WORD W_R SCND_CFG_BYTE_READ F_Cs0 HARD_RESET_ACTIVE CONF_ADD 1 FROM_FLASH_CNFG_WORD FROM_HOST_CNFG_WORD W_R THIRD_CFG_BYTE_READ F_Cs0 HARD_RESET_ACTIVE CONF_ADD 2 FROM_FLASH_CNFG_WORD FROM_HOST_CNFG_WORD W_R FOURTH_CFG_BYTE_READ F_Cs0 HARD_RESET_ACTIVE CONF_ADD 3 FROM_FLASH_CNFG_WORD FROM_HOST_CNFG_WORD W_R IF MPC_READ_BCSR...

Page 115: ...0 7 ELSE Data_Buff oe GND Do not assign Data Bus END IF D 0 SIZE0 Data_Buff 0 SIZE0 Move Data to Bus BCSR2_CS MPC_READ_BCSR_2 DSP reads external BCSR2 status Reset Logic Debounce the Abort NMI Soft Reset and HardReset buttons assign outputs SoftRstMachin Clk ResetEnsure q 18 SoftRstMachin Reset REGULAR_POWER_ON_RESET SoftRstMachin PushBtn RstSoft SoftReset SoftRstMachin Rst_True HardRstMachin Clk ...

Page 116: ... ToolDataBufEn ToolCs1 ToolCs2 DATA_HOLD q 0 AUX indication Use BCSR0 IF SRESET or REGULAR_POWER_ON_RESET or SIGNAL_LAMP_0 SIGNAL_LAMP_ON THEN SIG_LAMP0_OUT GND ELSE SIG_LAMP0_OUT VCC END IF IF HARD_RESET_ACTIVE or REGULAR_POWER_ON_RESET or SIGNAL_LAMP_1 SIGNAL_LAMP_ON THEN SIG_LAMP1_OUT GND ELSE SIG_LAMP1_OUT VCC END IF Eguations for FETH CODEC T1 ch 1 4 enables IF CODEC_EN FETHIEN T1_234EN T1_1E...

Page 117: ...T GND ELSE FETH_RST_OUT VCC END IF RS232 Transceivers Enable Use BCSR1 IF RS232En_1 RS232_1_ENABLED THEN RS232EN_1_OUT GND RS232 1 active ELSE RS232EN_1_OUT VCC standby END IF IF RS232En_2 RS232_2_ENABLED THEN RS232EN_2_OUT GND RS232 2 active ELSE RS232EN_2_OUT VCC standby END IF T1 E1 Framer CS IF FrmCs_In GND THEN FrmCs_OUT GND ELSE FrmCs_OUT VCC END IF IF FrmRst GND HARD_RESET_ACTIVE THEN FrmRs...

Page 118: ...ARD_RESET_ACTIVE BNK_TRI 0 TRI MODCK_TRI 3 HARD_RESET_ACTIVE MODCK_BNK 0 2 BNK_TRI 0 2 BOOT FROM SERIAL EEPROM EEPROM_ENABLE SBOOT_EN BTM0 AND BTM1 IF FETHIEN AND EEPROM_ENABLE THEN SBOOTEN_OUT GND boot from serial EEPROM ELSE SBOOTEN_OUT VCC END IF DRIVE PORESET IMPULSE RECONFIG USING BCSR4 DivEn s GND DivEn r GND DivEn prn MPC_WRITE_BCSR_4 D 0 1 B 10 END_OF_WD_TIMER Preset to FF when write b 10 ...

Page 119: ...IMER4 g StartStopWD q WD_TIMER5 g StartStopWD q WD_TIMER6 g StartStopWD q WD_TIMER7 g StartStopWD q WD_TIMER8 g StartStopWD q WD_TIMER2 clk WD_TIMER1 dv16 Cascade WD_TIMER3 clk WD_TIMER2 dv16 Cascade WD_TIMER4 clk WD_TIMER3 dv16 Cascade WD_TIMER5 clk WD_TIMER4 dv16 Cascade WD_TIMER6 clk WD_TIMER5 dv16 Cascade WD_TIMER7 clk WD_TIMER6 dv16 Cascade WD_TIMER8 clk WD_TIMER7 dv16 Cascade HRESET_FEdge cl...

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