Motorola MPC860 PowerQUICC, User Manual

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32-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
that the core knows buffers have been serviced. The buffers themselves can be placed in
external memory or in any unused parameter area of the dual-port RAM.
Figure 32-12. I
2
C Memory Structure
32.7.1 I 2 C Buffer Descriptors (BDs)
Receive and transmit buffer descriptors report information about each buffer transferred
and whether a maskable interrupt should be generated. Each 64-bit BD, shown in
Figure 32-13 and Figure 32-14, has the following structure:
¥ The half word at 0 contains status and control bits. The CPM updates the
status bits after the buffer is sent or received.
¥ The half word at 2 contains the data length (in bytes) that is sent or received.
Ñ For an RxBD, this is the number of octets the CPM writes into this RxBDÕs
buffer once the descriptor closes. The CPM updates this Þeld after the received
data is placed into the associated buffer. Memory allocated for this buffer should
be no smaller than MRBLR.
Ñ For a TxBD, this is the number of octets the CPM should transmit from its buffer.
Normally, this value should be greater than zero. The CPM never modiÞes this
Þeld.
¥ The word at 4 points to the beginning of the buffer.
Ñ For an RxBD, the pointer must be even and can point to internal or external
memory.
Ñ For a TxBD, the pointer can be even or odd. The buffer can reside in internal or
external memory.
32.7.1.1 I
2
C Receive Buffer Descriptor (RxBD)
Using RxBDs, the CPM reports on each buffer received, closes the current buffer, generates
a maskable interrupt, and starts receiving data in the next buffer when the current one is full.
STATUS AND CONTROL
DATA LENGTH
BUFFER POINTER
STATUS AND CONTROL
DATA LENGTH
BUFFER POINTER
TX BUFFER
I
2
C RXBD TABLE POINTER
(RBASE)
RX BUFFER
DUAL-PORT RAM EXTERNAL MEMORY
TXBD TABLE
RXBD TABLE
TX BUFFER
I2C TXBD TABLE POINTER
(TBASE)
I2C RXBD TABLE
I2C TXBD TABLE