29-6
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part V. The Communications Processor Module
29.4.2 Synchronization and the TSA
A transparent-mode SCC using the time-slot assigner can synchronize either on a
user-deÞned in-line pattern or by inherent synchronization.
Note that when using the TSA, a newly-enabled transmitter sends from 10 to 15 frames of
idles before sending the actual transparent data due to start-up requirements of the TDM.
Therefore, when loopback testing through the TDM, expect to receive several bytes of 0xFF
before the actual data.
29.4.2.1 In-line Synchronization Pattern
The receiver can be programmed to begin receiving data into the receive buffers only after
a speciÞed data pattern arrives. To synchronize on an in-line pattern:
¥
Set GSMR_H[SYNL].
¥
Program the DSR with the desired pattern.
¥
Clear GSMR_H[CDP].
¥
Set GSMR_H[CTSP, CTSS, CDS].
If GSMR_H[TXSY] is also used, the transmitter begins transmission eight clocks after the
receiver achieves synchronization.
29.4.2.2 Inherent Synchronization
Inherent synchronization assumes synchronization by default when the channel is enabled;
all data sent from the TDM to the SCC is received. To implement inherent synchronization:
¥
Set GSMR_H[CDP, CDS, CTSP, CTSS].
If these bits are not set, the received bit stream will be bit-shifted. The SCC loses the Þrst
received bit because CD and CTS are treated as asynchronous signals.
29.5 CRC Calculation in Transparent Mode
The CRC calculations follow the ITU/IEEE standard. The CRC is calculated on the
transmitted data stream; that is, from lsb to msb for non-bit-reversed (GSMR_H[REVD] =
0) and from msb to lsb for bit-reversed (GSMR_H[REVD] = 1) transmission. The
appended CRC is sent msb to lsb.When receiving, the CRC is calculated as the incoming
bits arrive. The optional reversal of data (GSMR_H[REVD] = 1) is done just before data is
stored in memory (after the CRC calculation).
29.6 SCC Transparent Parameter RAM
For transparent mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as
in Table 29-2.
Summary of Contents for MPC860 PowerQUICC
Page 3: ...MPC860UM AD 07 98 REV 1 MPC860 PowerQUICC ª UserÕs Manual ...
Page 36: ...xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...
Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
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Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
Page 326: ...IV vi MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
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