Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 28. SCC Ethernet Mode 28-25
Part V. The Communications Processor Module
Data length and buffer pointer Þelds are described in Section 22.2, ÒSCC Buffer
Descriptors (BDs).Ó
28.21 SCC Ethernet Event Register (SCCE)/Mask
Register (SCCM)
The SCC event register (SCCE) is used as the Ethernet event register to generate interrupts
and report events recognized by the Ethernet channel. When an event is recognized, the
Ethernet controller sets the corresponding SCCE bit. Interrupts are enabled by setting, and
masked by clearing, the equivalent bits in the Ethernet mask register (SCCM). SCCE bits
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared
before the CPM clears the internal interrupt request.
Table 28-9 describes SCCE and SCCM Þelds.
10Ð13 RC Retry count. Indicates the number of retries required before the frame was sent successfully. If RC =
0, the frame was sent correctly the Þrst time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15
retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then 15 or
more retries were required. The controller writes this Þeld after it successfully sends the buffer.
14 UN Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the
buffer. The Ethernet controller writes UN after it Þnishes sending the buffer.
15 CSL Carrier sense lost. Set when carrier sense is lost during frame transmission. The Ethernet controller
writes CSL after it Þnishes sending the buffer.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ GRA Ñ TXE RXF BSY TXB RXB
Reset 0000_0000_0000_0000
R/W R/W
Addr 0xA10 (SCCE1)/0xA34 (SCCM1); 0xA30 (SCCE2)/0xA34 (SCCM2)
0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4)
Figure 28-11. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
Table 28-9. SCCE/SCCM Field Descriptions
Bits Name Description
0Ð7 Ñ Reserved, should be cleared.
8 GRA Graceful stop complete. Set as soon the transmitter Þnishes any frame that was in progress when a
GRACEFUL STOP TRANSMIT
command was issued. It is set immediately if no frame was in progress.
9Ð10 Ñ Reserved, should be cleared.
11 TXE Set when an error occurs on the transmitter channel.
12 RXF Rx frame. Set when a complete frame has been received on the Ethernet channel.
Table 28-8. SCC Ethernet Receive TxBD Status and Control Field Descriptions
Bits Name Description