Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-7
Part V. The Communications Processor Module
20.3.3 IDMA Registers
Each IDMA channel has a DMA channel mode register (DCMR), an IDMA status register
(IDSR) and corresponding mask register (IDMR) that contain global channel parameters.
20.3.3.1 DMA Channel Mode Registers (DCMR)
Located in each IDMAÕs parameter RAM, the DMA channel mode registers (DCMR)
conÞgure the peripheral port size, the source and destination type of the transfer, and the
address mode (cycle mode) of the IDMA channels. Figure 20-5 shows the register format.
1
IDMA1 base = IMMR + 0x3CC0
IDMA2 base = IMMR + 0x3DC0
0x08 DAPR Word Destination data pointer (internal-use). Points to the next destination byte to be
written. The CP initializes DAPR to the BDÕs destination buffer pointer, and
increments it automatically if the destination is memory (DCMR[S/D] = 0b0x).
0x0C IBPTR Hword Current IDMA BD pointer. If the IDMA channel is idle, IBPTR points to the next
valid BD in the table. After a reset, or when the end (wrap bit) of the BD table is
reached, the CP wraps IBPTR back to IBASE.
0x0E WRITE_SP Hword Internal-use
0x10 S_BYTE_C Word Internal source byte count
0x14 D_BYTE_C Word Internal destination byte count
0x18 S_STATE Word Internal state
0x1C ITEMP 4 Words Temp data storage
0x2C SR_MEM Word Data storage for peripheral write
0x30 READ_SP Hword Internal-use
0x32 Ñ Hword Difference between source and destination residue
0x34 Ñ Hword Temp storage address pointer
0x36 Ñ Hword SR_MEM byte count
0x38 D_STATE Word Reserved. Internal state used by CP
¥ Notes: Boldfaced items must be initialized by the user before enabling an IDMA channel. The remaining
parameters are used by the CP only.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ SIZE S/D SC
Reset 0 0 0 0
R/W R R/W R/W R/W
Addr IDMA x Base + 0x02
Figure 20-5. DMA Channel Mode Register (DCMR)
Table 20-4. IDMA Parameter RAM Memory Map (Continued)