Motorola MPC860 PowerQUICC, User Manual, Page: 486 / 1106

16-60 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
4. DeÞne the UPM parameters that control the memory system in the following
sequence. For additional details, see Table 16-19.
Ñ Program the RAM array using MCR and MDR. The RAM word must be written
into the MDR before a WRITE command is issued to the MCR. Repeat this step
for all RAM word entries.
Ñ Initialize the option and base registers of the speciÞc bank according to the
address mapping of the DRAM device chosen.
Ñ Use ORx[MS] to select the machine to control the cycles. Notice that ORx[SAM]
determines address multiplexing for the Þrst clock cycle and subsequent cycles
are controlled by the UPM RAM words. Also notice that the AMX Þeld in the
UPM RAM word controls address multiplexing for the next clock cycle rather
than the current one.
Ñ Program MAMR to select the number of columns and refresh timer parameters.
Table 16-19. UPMA Register Settings
Register Field Value Comments
BR1 MS 10 Selects UPMA
PS 00 Selects 32-bit bus width
WP 0 Allows read and write accesses
MPTPR PTP 00000010 Prescaler divided by two
MAMR PTA 00001100 15.6
m
s at a 25-MHz clock
PTAE 1 Enables periodic timer A
AMA 001 Selects nine column address pins
DSA 01 Selects two disable timer clock cycles
GPLA4DIS 0 Disables the UPWAITA signal
RLFA 0011 Selects three loop iterations for read
WLFA 0011 Selects three loop iterations for write
OR1 SAM 1 Selects column address on Þrst cycle
BIH 0 Supports burst accesses