Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 16. Memory Controller 16-43
Part IV. Hardware Interface
16.6.4.6 Exception Pattern Entry (EXEN)
When the MPC860 under UPM control begins accessing a memory device, the external
device may assert TEA, SRESET, or HRESET. An exception occurs when one of these
signals is asserted by an external device and the MPC860 begins closing the memory cycle
transfer. When one of these exceptions is recognized and EXEN in the RAM word is set,
the UPM branches to the special exception start address (EXS) and begins operating as the
pattern deÞned there speciÞes. See Table 16-14. The user should provide an exception
pattern to deassert signals controlled by the UPM in a controlled fashion. For DRAM
control, a handler should negate RAS and CAS to prevent data corruption. If EXEN = 0,
exceptions are deferred and execution continues. After the UPM branches to the exception
start address, it continues reading until the LAST bit is set in the RAM word.
16.6.4.7 Address Multiplexing (AMX)
To support many devices with multiplexed address signals, the upper address signals can
be driven on the lower address lines. MxMR[AMA] and MxMR[AMB] control which
upper address signals are on which lower address signals.
Note that this feature of internally multiplexing address signals should only be used in a
system where the MPC860 is the only external bus master. If other devices can be bus
masters, address multiplexing must be done in external logic. One of the UPMÕs output
signals can be used to control this external multiplexing logic; GPL5 has been speciÞcally
enhanced for this. See the description of GPL5 in Section 16.6.4.4, ÒGeneral-Purpose
Signals (GxTx, GOx).Ó
ORx[SAM] and the AMX Þeld of the RAM words determine when the multiplexing occurs.
ORx[SAM] controls address multiplexing for the Þrst clock cycle. The AMX Þeld in the
RAM word determines the multiplexing for subsequent clock cycles. As an address is
driven off of the falling edge of GCLK1Ð50, the address in a particular clock cycle is
actually controlled by the previous RAM word, as shown in Figure 16-43.
The AMX Þeld can be used to output the contents of MAR on the address signals.
Figure 16-43 shows address multiplex timing.
Table 16-16. MxMR Loop Field Usage
Request Serviced Loop Field
Read single-beat cycle RLFx
Read burst cycle RLFx
Write single-beat cycle WLFx
Write burst cycle WLFx
Periodic timer expired TLFx