Motorola MPC860 PowerQUICC, User Manual

Page: 390 / 1106

14-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
before the next rising edge after it was sampled as asserted to avoid the detection of an error
for the next initiated bus cycle. TEA is an open-drain pin that allows the wire-OR of any
different sources of error generation.
14.4.10.1 RETRY
When an external device asserts RETRY during a bus cycle, the MPC860 enters a sequence
in which it terminates the current transaction, relinquishes bus ownership, and retries the
cycle using the same address, address attributes, and data (in the case of a write cycle).
Figure 14-29 shows that when the internal arbiter is enabled, MPC860 negates BB and
asserts BG in the clock cycle after RETRY is detected to allow any external master to gain
bus ownership. Normal arbitration resumes in the next clock cycle. If the external master
does not use the bus, the MPC860 initiates a new transfer with the same address and
attributes as before. In Figure 14-30 the same situation is shown where the MPC860 is
working with an external arbiter. In this case, in the clock cycle after RETRY is detected
asserted, BR and BB are negated together. Normal arbitration resumes one clock cycle later.
Figure 14-29. Retry Transfer TimingÐInternal Arbiter
CLKOUT
BR
BG (Output)
BB
A[0Ð31]
R/W
TSIZ[0Ð1]
BURST
TS
Data
TA
RETRY
Allow external master
to gain the bus
A A