Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 12. Reset 12-7
Part III. Configuration
(D[0Ð31] = 0x00000000). If the RSTCONF signal is asserted at sampling time, the
conÞguration is sampled from the data bus. If the RSTCONF signal is negated the internal
default value is selected. While HRESET and RSTCONF are asserted, the MPC860 weakly
pulls the data bus low, and the desired conÞguration is selected by driving the appropriate
bits high as shown in Figure 12-4.
Figure 12-4 shows a typical data bus conÞguration input circuit.
Figure 12-4. Data Bus Configuration Input Circuit
The conÞguration of the MPC860 following the assertion of PORESET is shown in Figures
4-2 through 4-4. While the PORESET input signal is being asserted, the core assumes the
default reset conÞguration (0x0000 0000). This changes when PORESET is negated or the
CLKOUT signal begins oscillation, and the desired hardware conÞguration is sampled
from the data bus every nine clock cycles on the rising edge of CLKOUT. The setup time
required for the data bus is 15 cycles and the maximum rise time of HRESET should be less
than six clock cycles. Refer to Section 12.3.2, ÒSoft Reset,Ó for more information.
Figure 12-5 shows a reset operation with a short PORESET signal assertion. Note that the
conÞguration of the MPC860 is determined from the signal levels driven on the D[0Ð31]
signals following the assertion of RSTCONF and the negation of HRESET.
MUX
DX (Data Line)
ConÞguration
Word
HRESET
RSTCONF
MPC860
NOTE: The value of the internal pulldown resistor is not speciÞed or guaranteed.
MPC860