MOTOROLA
Chapter 9. Memory Management Unit (MMU)
9-29
Part II. PowerPC Microprocessor Module
9.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0)
The DMMU RAM entry read register 0 (MD_RAM0), shown in Figure 9-21, contains the
physical page number and page attributes of an entry indexed by MD_CTR[DTLB_INDX].
This register is updated when any value is written to MD_CAM.
Table 9-20 describes MD_RAM0 Þelds.
24Ð26
PS
Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
27
SH
Shared page
0 This entry matches only if the ASID Þeld in the DTLB entry matches the value in M_CASID
1 ASID comparison is disabled for the entry
28Ð31
ASID
Address space ID of the DTLB entry to be compared with M_CASID[CASID]
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
RPN
Reset
Ñ
R/W
R
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
RPN
PS
APGI
G
WT
CI
Ñ
Reset
Ñ
R/W
R/W
SPR
825
Figure 9-21. DMMU RAM Entry Read Register 0 (MD_RAM0)
Table 9-20. MD_RAM0 Field Descriptions
Bits
Name
Description
0Ð19
RPN
Real (physical) page number
20Ð22
PS
Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
23Ð26
APGI
Access protection group inverted. Access protection group number in oneÕs complement format
27
G
Guarded memory attribute for the entry
0 Nonguarded memory
1 Guarded memory
Table 9-19. MD_CAM Field Descriptions (Continued)
Bits
Name
Description
Summary of Contents for MPC860 PowerQUICC
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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