Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 8. Instruction and Data Caches 8-21
Part II. PowerPC Microprocessor Module
match is found and the matched entry is valid, then it is a cache hit. If neither tag matches
or the matched tag is not valid, it is a cache miss.
The data path for the instruction cache and its surrounding logic are shown in Figure 8-9.
Figure 8-9. Instruction Cache Data Path
The 4-word burst buffer holds the last cache block received from the internal bus (the last
miss); the 4-word block buffer holds the last block retrieved from the instruction cache (the
last hit). Note that if one of these buffers contains the requested instruction, it is also
considered a cache hit. To minimize power consumption, the MPC860 can detect that one
of the buffers contains the requested instruction and service the instruction request from the
buffers without activating the instruction cache array.
4-Word
To Instruction
Internal Data Bus
Set
Address [21Ð27]
4-Word
Address [28Ð29]
Instruction Cache
Array Decoder
128
32
Burst
Buffer
128
128
128
Stream
Hit
Mux
2->1
Word
Select
Mux
4->1
128
Data
Bypass
Mux
2->1
32
32
Sequencer
Cache
Block
Buffer