7-4
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part II. PowerPC Microprocessor Module
When multiple exception conditions exist, only the highest priority exception is taken, as
shown in Table 7-3.
7.1.2 PowerPC-DeÞned Exceptions
The following sections describe the exceptions as they are deÞned by the OEA, and
describes how they are implemented on the MPC860.
1
The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second
instruction. This, of course, refers to this second instruction.
2
MPC860-speciÞc exception.
3
Exclusive for any one instruction.
Table 7-2. Instruction-Related Exception Detection Order
Number
Exception Type
Cause
1
Trace
Trace bit asserted
1
2
ITLB miss
2
Instruction MMU TLB miss
3
ITLB error
Instruction MMU protection/translation error
4
Machine check
Fetch error
5
Debug instruction breakpoint
Match detection
6
Software emulation exception
Attempt to invoke unimplemented feature
7
3
Privileged instruction
Attempt to execute privileged instruction in user mode
Alignment Load/store
checking
System call
sc
instruction
Trap
Trap instruction
8
DTLB miss
Data TLB miss
9
Data TLB protection/translation error
10
Machine check
Load or store access error
11
Match detection
Table 7-3. Exception Priority
Priority
Exception Type
Cause
1
Development port nonmaskable interrupt
Signal from the development port
2
System reset interrupt
IRQ0 assertion
3
Instruction-related exceptions
Instruction processing
4
Peripheral breakpoint request or development port maskable interrupt Breakpoint signal from any peripheral
5
External interrupt (masked if MSR[EE] = 0)
Signal from the interrupt controller
6
Decrementer interrupt (masked if MSR[EE] = 0)
Decrementer request
Summary of Contents for MPC860 PowerQUICC
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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