Motorola MPC860 PowerQUICC, User Manual

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Part I. Overview
MOTOROLA Chapter 3. Hardware Interface Overview 3-3
3.1 System Bus Signals
The MPC860 system bus consists of all signals that interface with the external bus. Many
of these signals perform different functions, depending on how the user assigns them. The
following input and output signals are identiÞed by their abbreviation.
The MPC860 bus is a synchronous, burstable bus that can support multiple masters. Signals
driven on this bus are required to make the setup and hold time relative to the bus clockÕs
rising edge. The MPC860 architecture supports byte, half-word, and word operands
allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles
controlled by the size outputs (TSIZ0, TSIZ1). Access to 16- and 8-bit ports is done for
slaves controlled by the memory controller.
3.2 System Bus Signals
The MPC860 system bus consists of all signals that interface with the external bus. Many
of these signals perform different functions, depending on how the user assigns them. The
input and output signals, shown in Table 3-1, are identiÞed by their abbreviation. Signal pin
numbers can be found in Figure 13-2 and Figure 13-3.
Table 3-1. Signal Descriptions
Name Type Description
A[0Ð31] Bidirectional
Three-state
Address BusÑThis signal provides the address for the current bus cycle. A0 is the
most-signiÞcant signal for this bus. The bus is output when an internal master starts
a transaction on the external bus. The bus is input when an external master starts a
transaction on the bus.
TSIZ0
REG Bidirectional
Three-state
Transfer Size 0ÑWhen accessing a slave in the external bus, this signal is used
(together with TSIZ1) by the bus master to indicate the number of operand bytes
waiting to be transferred in the current bus cycle.
TSIZ0 is an input when an external master starts a bus transaction.
RegisterÑWhen an internal master initiates an access to a slave controlled by the
PCMCIA interface, REG is output to indicate which space in the PCMCIA card is
accessed.
TSIZ1 Bidirectional
Three-state
Transfer Size 1ÑThis signal is used (with TSIZ0) by the bus master to indicate the
number of operand bytes waiting to be transferred in the current bus cycle.
The MPC860 drives TSIZ1 when it is bus master. TSIZ1 is input when an external
master starts a bus transaction.
RD/WR Bidirectional
Three-state
Read/WriteÑThis signal is driven by the bus master to indicate the direction of the
busÕs data transfer. A logic one indicates a read from a slave device and a logic zero
indicates a write to a slave device.
The MPC860 drives this signal when it is bus master. This signal is input when an
external master initiates a transaction on the bus.
BURST Bidirectional
Three-state
Burst TransactionÑThis signal is driven by the bus master to indicate that the current
initiated transfer is a burst.
The MPC860 drives this signal when it is bus master. This signal is input when an
external master initiates a transaction on the bus.