Motorola MCP750HA Series Installation And Use Manual Download Page 101

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Using PPCBug

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5-9

IOT

I/O Teach for Configuring Disk Controller

Load S-Records from Host

Macro Define/Display

NOMA

Macro Delete

MAE

Macro Edit

MAL

Enable Macro Listing

NOMAL

Disable Macro Listing

MAR

Load Macros

MAW

Save Macros

MD, MDS

Memory Display

System Menu

Memory Modify

MMD

Memory Map Diagnostic

Memory Set

Memory Write

NAB

Automatic Network Boot

NBH

Network Boot Operating System, Halt

NBO

Network Boot Operating System

NIOC

Network I/O Control

NIOP

Network I/O Physical

NIOT

Network I/O Teach (Configuration)

NPING

Network Ping

Offset Registers Display/Modify

Printer Attach

NOPA

Printer Detach

PBOOT

Bootstrap Operating System

Port Format

NOPF

Port Detach

PFLASH

Program FLASH Memory

Table 5-1. Debugger Commands (Continued)

Command

Description

Summary of Contents for MCP750HA Series

Page 1: ...MCP750HA Hot Swap CompactPCI Single Board Computer Installation and Use MCP750HA IH3 December 2000 ...

Page 2: ...ered trademarks of Motorola Inc PowerPC is a trademark of IBM Corporation and is used by Motorola Inc under license from IBM Corporation CompactPCI is a registered trademark of PCI Industrial Computer Manufacturers Group All other products mentioned in this document are trademarks or registered trademarks of their respective holders ...

Page 3: ...ide the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the po...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur M...

Page 5: ...oned requirements A proper installation in a CE marked system will maintain the required EMC safety performance In accordance with European Community directives a Declaration of Conformity has been made and is on file within the European Union The Declaration of Conformity is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the ...

Page 6: ...tricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights ...

Page 7: ...Preparation 1 6 Flash Bank Selection J9 1 6 Hardware Installation 1 9 ESD Precautions 1 9 Compact FLASH Memory Card Installation 1 9 RAM300 Memory Mezzanine Installation 1 11 PMC Module Installation 1 13 MCP750HA Module Installation 1 15 System Considerations 1 18 MCP750HA Module Power Requirements 1 18 CHAPTER 2 Operating Instructions Introduction 2 1 Applying Power 2 1 Memory Maps 2 2 Processor ...

Page 8: ...ce 3 10 Asynchronous Serial Ports 3 10 Parallel Port Printer Interface 3 11 Floppy Disk Tape Drive Controller 3 11 Keyboard and Mouse Interface 3 12 PCI Peripheral Bus Controller PBC 3 12 EIDE Series Termination 3 13 Real Time Clock NVRAM Watchdog Timer Function 3 13 Programmable Timers 3 14 Raven General Purpose Timers 3 14 Raven Watchdog Timers 3 15 M48T559 Watchdog Timer 3 15 Interval Timers 3 ...

Page 9: ...actPCI HSC User I O Connector J3 4 4 Local Bus Expansion Connector J4 4 5 User I O Connector J5 4 6 PCI Mezzanine Card Connectors J11 J12 J13 J14 4 7 Front USB Connectors J17 J18 4 10 10BaseT 100BaseTX Connector J8 4 10 COM1 Connector J15 4 11 Reset and Abort Header J21 4 12 Debug Connector J16 4 12 DRAM Mezzanine Connector J7 4 16 EIDE Compact FLASH Connector J20 4 19 CHAPTER 5 PPCBug PPCBug Over...

Page 10: ... B Hardware Preparation and Installation for TMCP700 Introduction B 1 Unpacking Instructions B 1 TMCP700 Transition Module Preparation B 1 Serial Ports 1 and 2 B 4 Configuration of Serial Ports 3 and 4 B 4 ESD Precautions B 9 TMCP700 Transition Module Installation B 9 TMCP700 Transition Module B 11 CompactPCI Connectors J3 J4 J5 B 12 Serial Ports 1 and 2 J10 J11 TMCP700 I O Mode B 12 Serial Ports ...

Page 11: ...xi PMC I O Connectors J2 J21 B 18 APPENDIX C Related Documentation Motorola Computer Group Documents C 1 Manufacturers Documents C 2 Related Specifications C 3 ...

Page 12: ...cement on MCP750HA 1 10 Figure 1 4 RAM300 Placement on MCP750HA 1 12 Figure 1 5 PMC Module Placement on MCP750HA 1 14 Figure 1 6 MCP750HA Board Insertion Sequence 1 17 Figure 2 1 PPCBug System Startup 2 2 Figure 3 1 MCP750HA Block Diagram 3 4 Figure 3 2 Active Passive System 3 7 Figure 3 3 Serial Port Signal Multiplexing 3 19 Figure 3 4 MX Signal Timings 3 21 ...

Page 13: ...e 4 5 J5 User I O Connector 4 6 Table 4 6 PCI Mezzanine Card Connector 4 7 Table 4 7 PCI Mezzanine Card Connector 4 9 Table 4 8 USB 0 Connector J18 4 10 Table 4 9 USB 1 Connector J17 4 10 Table 4 10 10BaseT 100BaseTX Connector J8 4 11 Table 4 11 COM1 Connector J15 4 11 Table 4 12 Reset Abort Header J21 4 12 Table 4 13 Debug Connector J16 4 12 Table 4 14 DRAM Mezzanine Connector J7 4 16 Table 4 15 ...

Page 14: ...P700 B 14 Table B 4 Keyboard Mouse Connector J16 TMCP700 B 15 Table B 5 EIDE Connector J15 B 16 Table B 6 Floppy Connector J17 B 17 Table B 7 5Vdc Power Connector J14 B 18 Table B 8 Speaker Output Connector J13 B 18 Table B 9 PMC I O Connector J2 B 18 Table B 10 PMC I O Connector J21 B 20 Table C 1 Motorola Computer Group Documents C 1 Table C 2 Manufacturer s Documents C 2 Table C 3 Related Speci...

Page 15: ...2MB ECC DRAM 9MB FLASH MB L2 Cache MCP750HA 1242 F MPC750 233 MHz CPU 64MB ECC DRAM 9MB FLASH 1MB L2 Cache MCP750HA 1252 F MPC750 233 MHz CPU 128MB ECC DRAM 9MB FLASH 1MB L2 Cache MCP750HA 1262 F MPC750 233 MHz CPU 256MB ECC DRAM 9MB FLASH 1MB L2 Cache MCP750HA 233 F MPC750 366 MHz CPU NO DRAM 5MB FLASH 1MB L2 Cache MCP750HA 366 F MPC750HA 366 MHz CPU MCP750HA 366 K MPC750HA 366 MHz CPU KIT Date C...

Page 16: ...architecture Additionally it describes the monitor interactive command portion of the firmware and provides instructions on using the PPCBug debugger and the associated special commands A complete list of PPCBug commands is also included in this chapter Chapter 6 CNFG and ENV Commands outlines how to use the factory installed debug monitor PPCBug to modify certain parameters contained in the Power...

Page 17: ...r of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories ...

Page 18: ...xx CR represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d ...

Page 19: ...is used throughout this document to refer to all models of the MCP750HA or CPX750HA CPU based boards that employ hot swap capabilities Refer to the table on page xvii in the About This Manual section for a complete list of model numbers The MCP750HA is a single slot Hot Swappable CompactPCI board equipped with a PowerPC Series microprocessor The board can be purchased in a standard MCP750 or Hot S...

Page 20: ...PBC VT82C586B Serial P MC SLot RTC MK48T559 Super I O PC97307 Front Panel 10BT 100BTx Ethernet USB 1 USB 0 NVRAM ISA 33 MHz 32 64 bit PCI Bus WD J4 PCI PCI BRIDGE DEC21154 USB Clock Generator Reset Control Arbitration Control Flash DRAM Expansion 8MB Linear Flash up to 256MB of DRAM IDE USB 32 64 bit PMC Slot MPIC Controller SERIAL KEYBOARD MOUSE PARALLEL CIO z8536 ESCC Z85230 2 SYNC ASYNC ISA Reg...

Page 21: ...sis only MCP750HA modules are factory configured for I O handling via a TMCP700 transition module There are various MCP750HA models available that correspond to different memory configurations and processor speeds One transition module supports all configurations of the board Note Contact your local Motorola sales representative and or your designated sales systems engineer or distributor for the ...

Page 22: ...ansition modules MCP750HA Base Board Preparation and TMCP700 Transition Module Preparation Ensure CompactFLASH card is installed if required Compact FLASH Memory Card Installation Ensure memory mezzanines are properly installed on the board RAM300 Memory Mezzanine Installation Install PMC Module if required PMC Module Installation Install the MCP750HA in the chassis MCP750HA Module Installation In...

Page 23: ...ntegrated circuitry static discharge can damage circuits Note that the debugger initializes the MCP750HA Using PPCBug Note You may also wish to obtain the PPCBug Firmware Package User s Manual and the CPX750HA PPCBug Firmware User s Manual listed in Appendix C Related Documentation Initialize the system clock Using PPCBug Debugger Commands and the SET command Examine and or change environmental pa...

Page 24: ...ace modules on the base board itself or the associated transition module MCP750HA Base Board Preparation Figure 1 2 shows the location of switches jumpers connectors and LED indicators on the MCP750HA Manually configured items on the base board include a flash bank selection J9 For additional information on the configured items of the transition module refer to the section entitled TMCP700 Transit...

Page 25: ...sh Bank A 8MB memory on the RAM300 mezzanine install a jumper on header J9 across pins 1 and 2 To enable Flash Bank B 1MB memory on the base board install a jumper on header J9 across pins 2 and 3 J10 Factory Use Only Header J10 is an ISP program download cable connection that is left on the board for MCG factory use only 3 2 1 3 2 1 Flash Bank A Enabled Flash Bank B Enabled 1MB on base board J9 J...

Page 26: ...es Headers Connectors and LEDs 2641 9910 10 100 BASE T 1 J15 189 190 2 1 J7 USB 1 CPI ABT BFL RST CPU PCI MEZZANINE CARD 2 DS4 COM 1 4 1 XU1 CPCI J11 49 50 3 J8 S2 S1 1 DS2 DS1 DS3 J17 J18 4 1 1 5 6 9 8 2 7 1 1 2 J12 49 50 1 2 J13 49 50 1 2 J14 49 50 XU2 USB 0 J9 J5 J4 J3 J2 J1 J20 189 190 2 1 J16 3 1 J21 1 8 J10 ...

Page 27: ...a strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules are extremely sensitive to ESD After removing a component from the system or its protective wrapper place the component on a grounded static free surface In handling a board place it component side ...

Page 28: ...wer off and remove the AC cord or DC power lines from the system Remove the chassis or system cover s as necessary to access the compact PCI module Figure 1 3 Compact FLASH Placement on MCP750HA Caution Inserting or removing modules that are not HA capable with power applied may result in damage to module components Warning To prevent injury use extreme caution when handling testing and adjusting ...

Page 29: ...ard aligns with pin 1 of J20 6 Place the RAM300 mezzanine module on top of the base board The connector on the underside of the mezzanine should connect smoothly with the corresponding connector J7 on the MCP750HA 7 Insert the four short phillips head screws through the holes at the corners of the RAM300 mezzanine and into the standoffs on the MCP750HA Tighten the screws 8 Reinstall the MCP750HA a...

Page 30: ...out the procedure 2 If the DRAM is being installed in a non hot swap chassis perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the compact PCI module Figure 1 4 RAM300 Placement on MCP750HA Caution Inserting or removing memory mezzanine modules with power applied may ...

Page 31: ...of the RAM300 should connect smoothly with the corresponding connector J7 on the MCP750HA 5 Insert the four short phillips head screws through the holes at the corners of the RAM300 mezzanine and into the standoffs on the MCP750HA Tighten the screws 6 Reinstall the MCP750HA assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend the conn...

Page 32: ...n hot swap chassis perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the CompactPCI Figure 1 5 PMC Module Placement on MCP750HA Caution Inserting or removing PMC modules with power applied may result in damage to module components Warning To prevent injury use extreme...

Page 33: ... through the holes on the bottom side of the MCP750HA and the PMC front bezel and into rear standoffs Tighten the screws 7 Reinstall the MCP750HA assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 8 If the PMC module was installed in a non hot swap chassis replace the chassis or system cover s reconnect the system to ...

Page 34: ...pactPCI system slot in order to provide clocks and arbitration to the other slots The system slot is identified with a triangle symbol which is marked on the backplane Some CompactPCI subracks may have a red guide rail to mark the system slot 4 Set the VIO on the backplane to either 3 3V or 5V depending upon your system s signaling requirements Caution Ensure the backplane does not bus J3 J4 or J5...

Page 35: ...6 MCP750HA Board Insertion Sequence 6 Replace the chassis or system cover s making sure that no cables are pinched Cable the peripherals to the panel connectors For non hot swap chassis reconnect the system to the AC or DC power source and turn the equipment power on Step 1 Step 2 Step 3 ...

Page 36: ...ware console should be set up as follows Eight bits per character One stop bit per character Parity disabled no parity Baud rate of 9600 baud 9600 is the default baud rate for serial ports on MCP750HA boards After power up you can reconfigure the baud rate if you wish using the PPCBug PF Port Format command via the command line interface Whatever the baud rate some type of hardware handshaking eit...

Page 37: ...up or system reset The firmware initializes the devices on the SBC module in preparation for booting the operating system The firmware is shipped from the factory with an appropriate set of defaults In most cases there is no need to modify the firmware configuration before you boot the operating system Figure 2 1 shows the basic initialization process that takes place during PowerPC system startup...

Page 38: ...d RESET switches and four LED status indicators BFL CPU PCI CPCI For additional information on front panel operation refer to Chapter 3 Functional Description Memory Maps There are three points of view for memory maps STARTUP SYSTEM INITIALIZATION CONSOLE DETECTION OPERATING SYSTEM RUN SELF TESTS IF ENABLED AUTOBOOT IF ENABLED 11734 00 9702 ...

Page 39: ...ry map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers At system power up or reset a default processor memory map takes over Default Processor Memory Map The default processor memory map that is valid at power up or r...

Page 40: ...mpatible memory maps refer to the MCP750 Single Board Computer Programmer s Reference Guide MCP750A PG listed in Appendix C Related Documentation PCI Local Bus Memory Map The PCI memory map is controlled by the Raven ASIC and by the 21154 PCI to PCI bridges The Raven and the PCI to PCI bridges adjust system mapping to suit a given application via programmable map decoder registers No default PCI m...

Page 41: ...o the CompactPCI bus secondary bus All devices on the CompactPCI bus must be configured for addressing within this defined range Conversely these registers also define the addresses for which transactions will be forwarded upstream Any CompactPCI bus address generated by a CompactPCI bus master not in the defined memory range will be forwarded upstream to the Primary PCI bus There is no address tr...

Page 42: ...performing interrupt handling Sources of interrupts may be any of the following The Raven ASIC itself timer interrupts or transfer error interrupts The processor processor self interrupts The Falcon chip set memory error interrupts The PCI bus interrupts from PCI devices The CompactPCI bus interrupts from CompactPCI devices The CompactPCI expansion bus interrupts from HSC and expansion bus Power m...

Page 43: ... timer Reset function controlled by the SGS Thomson MK48T559 Watchdog Timer or the Raven Watchdog Timers 5 Port 92 Register via the PBC 6 CompactPCI Bus via the 21154 Bridge Control Register 7 Optional external reset from J5 pin A22 Table 2 2 PBC DMA Channel Assignments PBC Priority PBC Label Controller DMA Assignment 1 Channel 0 DMA1 Serial Port 3 Receiver Z85230 Port A Rx 2 Channel 1 Serial Port...

Page 44: ...little endian The following sections summarize how the MCP750HA handles software and hardware differences in big and little endian operations For further details on endian considerations refer to the MCP750 Single Board Computer Programmer s Reference Guide listed in Appendix C Related Documentation Table 2 3 Classes of Reset and Effectiveness Device Affected Reset Source Processor Raven ASIC Falc...

Page 45: ...programmed to operate in big endian mode with the processor and the memory subsystem In little endian mode the Raven reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done PCI Domain The PCI bus is inherently little endian All devices connected directly to the PCI bus operate in little endian mode re...

Page 46: ...Related Documentation You may also refer to this guide for a more detailed functional description of the MCP750HA Features The following table summarizes the features of the MCP750HA single board computers Table 3 1 MCP750HA Features Feature Description Microprocessor MPC750 PowerPC processor ECC DRAM 32MB 256MB on RAM300 module L2 cache memory Populated with 1MB on base board Flash Memory Two 32 ...

Page 47: ...ports 2 sync async ports via the transition module Parallel I O IEEE 1284 bidirectional parallel port PC87307 SIO via the transition module Ethernet I O 10BaseT 100BaseTX connection via the front panel PCI interface One IEEE P1386 1 PCI Mezzanine Card PMC slot one 110 pin CompactPCI connector J4 for PCI expansion Hot Swap bridge Keyboard mouse interface Support for keyboard and mouse input PC87307...

Page 48: ...ons provided from the ISA bus are two async and two sync async serial ports keyboard mouse a floppy disk controller printer port a real time clock and NVRAM The MCP750HA interfaces to a CompactPCI bus using a DEC 21154 PCI to PCI bridge device This device provides a 64 bit primary and a 64 bit secondary interface allowing full 64 bit data access between CompactPCI bus devices and the host PCI brid...

Page 49: ... Async Serial RTC PMC Slot 1 RTC DRAM Raven 32 64 Bit PCI Local Bus ISA SIO Peripheral Bus PCI to PCI Bridge 1 FLASH Falcon Falcon MPC750 L2 Cache Sys CSR ISA CSR ISA Local Resource Bus Bridge 2 IDE Bus Compact FLASH SRAM SROM USB 2 Sync Async 2 channels 2 channels Controller Serial FDD USB 1 Connector Expansion 60X System Bus Hot Swap Controller Interface ...

Page 50: ...0HA circuitry is powered The HLTY signal is driven true low to the CPCI bus J1 pin B4 when the 5 0VDC 3 3VDC 12VDC and 12VDC input power supplies are all within tolerance This can be used as a status indicator CompactPCI Interface The CompactPCI bus interface will support up to 7 CompactPCI peripheral cards The CompactPCI bus interface is provided using the DEC 21154 PCI to PCI bridge chip This de...

Page 51: ...ary bus signalling voltage is tied to the CPCI bus VIO so the MCP750HA is a universal board that may operate in a 3 3V or 5V chassis PCI Expansion Connector J4 The expansion connector can be used to route the local PCI bus to a secondary PCI to PCI bridge In addition signals needed by the Hot Swap Controller Bridge Module are routed through J3 Refer to the chassis specific information found in the...

Page 52: ...his case live insertion of a MCP750HA must not disrupt the active CPCI bus The bus ownership is automatically established by the hot swap control circuitry in non high availability systems The backplane must leave the control lines J3 A15 J3 A16 J3 A17 and J3 A18 as no connects in non high availability implementations Pull up resistors located on the MCP750HA will then allow for normal PCI to PCI ...

Page 53: ...ECchip 21140 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports 10BaseT 100BaseTX connections The balanced differential transceiver lines are coupled via on board transformers The MCP750HA routes its 10BaseT 100BaseTX lines to an RJ45 connector on the front panel Every MCP750HA is assigned an Ethernet station address The address is 08003E2xxxxx where xxxxx is the uni...

Page 54: ...factory it should contain the proper SROM data for the MCP750HA which has 10BaseT 100 BaseTX Ethernet connections There should not be a need to change the SROM contents For the pin assignments of the 10BaseT 100BaseTX connector refer to Table 4 11 on page 4 11 PCI Mezzanine Interface A key feature of the MCP750HA family is the Peripheral Component Interconnect PCI bus In addition to the on board l...

Page 55: ...intend to use PC97307 ISA Super I O Device The MCP750HA uses the PC97307 ISA Super I O device from National Semiconductor to provide the following Two asynchronous serial ports Parallel port via transition module Floppy disk drive support via transition module A PS 2 keyboard and mouse interface via transition module A parallel printer port interface Asynchronous Serial Ports The Super I O device ...

Page 56: ...A I O base address of 3BC This default configuration also assigns the parallel port to Peripheral Bus Controller PBC interrupt request line IRQ7 The default configuration can be changed by reprogramming the ISA Super I O device For additional programming information refer to the PCI and ISA bus discussions in the MCP750 Single Board Computer Programmer s Reference Guide and to the vendor documenta...

Page 57: ...o the TMCP700 Transition Module Installation and Use manual for details PCI Peripheral Bus Controller PBC The MCP750HA uses the VIA Technologies VT82C586 Peripheral Bus Controller PBC to supply the interface between the PCI local bus and the ISA IDE and USB systems I O bus illustrated in Chapter 1 Hardware Preparation and Installation The PBC controller provides the following functions ISA Industr...

Page 58: ...PBC controller via the transition module or a domain specific EIDE connector on the backplane Refer also to Chapter 4 Connector Pin Assignments The resistance values are given in the following table Real Time Clock NVRAM Watchdog Timer Function The MCP750HA employs an ST Microelectronics surface mount M48T559 RAM and clock chip to provide 8KB of non volatile static RAM a real time clock and a watc...

Page 59: ...rates no interrupts Although the M48T559 is an 8 bit device 8 16 and 32 bit accesses from the ISA bus to the M48T559 are supported Refer to the MCP750 Single Board Computer Programmer s Reference Guide and to the M48T559 data sheet for detailed programming and battery life information Programmable Timers Among the resources available to the local processor are a number of programmable timers Timer...

Page 60: ...must be disabled or reloaded by software to prevent a timeout Software may reload a new timer value or force the timer to reload a previously loaded value To disable or load reload a timer requires a two step process The first step is to write the pattern 55 to the timer register key field which will arm the timer register to enable an update The second step is to write the pattern AA to the key f...

Page 61: ...ns Interface The MCP750HA uses a Zilog Z85230 Enhanced Serial Communications Controller ESCC to implement the two serial communications interfaces which are routed through the transition module The Z85230 supports synchronous SDLC HDLC and asynchronous protocols The MCP750HA hardware supports asynchronous serial baud rates of 110B s to 38 4 KB s Each interface supports the CTS DCD RTS and DTR cont...

Page 62: ...536 CIO Device The Z8536 CIO device complements the Z85230 ESCC by supplying modem control lines not provided by the Z85230 ESCC In addition the Z8536 CIO device has three independent 16 bit counters timers The Z85230 receives a 5 MHz clock input MCP750HA Board Identifier The MCP750HA CPU board is uniquely identified by the following registers The CPU Configuration Register is an 8 bit register lo...

Page 63: ... set there is no on board synchronous serial support the ESCC is not present If cleared the Z85230 ESCC is installed and there is on board support for synchronous serial communication PMC1P PMC slot 1 present If set no PCI mezzanine card is installed in PMC slot 1 If cleared PMC slot 1 contains a PCI mezzanine card LANP Ethernet present If set no Ethernet transceiver interface is installed If clea...

Page 64: ...arent to the software The block diagram for the signal multiplexing is shown in Figure 3 3 Figure 3 3 Serial Port Signal Multiplexing Signal Multiplexing MX There are four pins that are used for the MX function MXCLK MXSYNC MXDO and MXDI MXCLK is the 10 MHz bit clock for the time multiplexed data lines MXDO and MXDI MXSYNC is asserted for one bit time at Time Slot 15 by the MCP750HA board MXSYNC i...

Page 65: ... MXDO by using the rising edge of the MXCLK MXDI is sampled at the rising edge of MXCLK the transition module synchronizes MXDI with MXCLK s rising edge The timing relationships among MXCLK MXSYNC MXDO and MXDI are shown in Figure 3 4 Table 3 5 Multiplexing Sequence of the MX Function MXDO From MCP750HA MXDI From TMCP700 TIME SLOT SIGNAL NAME TIME SLOT SIGNAL NAME 0 RTS3 0 CTS3 1 DTR3 1 DSR3 MID1 ...

Page 66: ...nterrupt signal reaches the processor module via ISA bus interrupt line IRQ8 The signal is also available at pin PB7 of the Z8536 CIO device which handles various status signals serial I O lines and counters The interrupter connected to the ABORT switch is an edge sensitive circuit filtered to remove switch bounce RESET RST Switch S1 The RESET switch resets all onboard devices and generates a Comp...

Page 67: ...pin assignments for the header Front Panel Indicators DS1 DS4 There are four LEDs on the MCP750HA front panel BFL DS2 yellow Board Failure lights when the BRDFAIL signal line is active CPU DS4 green CPU activity lights when the DBB Data Bus Busy signal line on the processor bus is active PCI DS3 green PCI activity lights when the IRDY Initiator Ready signal line on the PCI bus is active This indic...

Page 68: ...ransition module The transition module contains a two pin jumper header J13 which allows the SPEAKER_OUT signal to be cabled to an external speaker to obtain a beep tone Table 3 6 Fuse Assignments Fuse Type Voltage Purpose J Number Fuse Rating U63 Electronic 3 3VDC for onboard voltage to J12 PMC connector and to J3 J4 Transition module connectors 9 8 Amps U63 Electronic 5VDC for onboard voltage an...

Page 69: ...provides the bridge between the MPC750 microprocessor bus and the PCI local bus Electrically the Raven chip is a 64 bit PCI connection Four programmable map decoders in each direction provide flexible addressing between the MPC750 microprocessor bus and the PCI local bus Flash Memory The MCP750HA base board has provision for 1MB of 16 bit Flash memory in two 8 bit sockets The RAM300 memory mezzani...

Page 70: ...trolled by the Falcon memory controller chip set The Falcon ASICs perform two way interleaving with double bit error detection and single bit error correction In addition to the ECC DRAM the RAM300 module supplies 8MB of additional soldered in 64 bit Flash memory A jumper header J9 tells the Falcon chip set where in memory to fetch the board reset vector Depending on the configuration of J9 resets...

Page 71: ...ders for PMC IO A 34 pin header for a floppy port A 2 pin header for speaker output Serial Interface Modules The synchronous serial ports on the TMCP700 are configured via Serial Interface Modules SIMs used in conjunction with the appropriate jumper settings on the transition module The SIMs are small plug in printed circuit boards which contain all the circuitry needed to convert a TTL level port...

Page 72: ... about the serial interface modules refer to the TMCP700 Transition Module Installation and Use manual listed in Appendix C Related Documentation SIMV35DCE V 35 DCE SIMV35DTE V 35 DTE SIMX21DCE X 21 DCE SIMX21DTE X 21 DTE Table 3 7 SIM Type Identification Continued Model Number Module Type ...

Page 73: ...ector J3 Local Bus Expansion Connector J4 User I O Connector J5 PCI Mezzanine Card PMC Connectors J11 J12 J13 J14 Front USB Connectors J17 J18 10BaseT 100BaseTX Connector J8 COM1 Connector J15 Reset Abort Header J21 Debug Connector J16 DRAM Memory Mezzanine Connector J7 EIDE Compact FLASH Memory Connector J20 Common Connectors The following tables describe connectors used with the same pin assignm...

Page 74: ...PCI Connector J1 ROW A ROW B ROW C ROW D ROW E 25 5V REQ64_L ENUM_L 3 3V 5V 25 24 AD1 5V VIO AD0 ACK64_L 24 23 3 3V AD4 AD3 5V AD2 23 22 AD7 GND 3 3V AD6 AD5 22 21 3 3V AD9 AD8 GND CBE0_L 21 20 AD12 GND VIO AD11 AD10 20 19 3 3V AD15 AD14 GND AD13 19 18 SERR_L GND 3 3V PAR CBE1_L 18 17 3 3V SDONE SBO_L GND PERR_L 17 16 DEVSEL_L GND VIO STOP_L LOCK_L 16 15 3 3v FRAME_L IRDY_L BD SEL_L TRDY_L 15 12 1...

Page 75: ...ct RSV No Connect RSV 21 20 CLK5 GND No Connect RSV GND No Connect RSV 20 19 GND GND No Connect RSV No Connect RSV No Connect RSV 19 18 No Connect BRSVP2A18 No Connect BRSVP2B18 No Connect BRSVP2C18 GND No Connect BRSVP2E18 18 17 No Connect BRSVP2A17 GND PRST_L REQ6_L GNT6_L 17 16 No Connect BRSVP2A16 No Connect BRSVP2B16 DEG_L GND No Connect BRSVP2E16 16 15 No Connect BRSVP2A15 GND FAL_L REQ5_L G...

Page 76: ...ND VIO CBE4_L PAR64 5 4 VIO No Connect BRSVP2B4 CBE7_L GND CBE6_L 4 3 CLK4 GND GNT3_L REQ4_L GNT4_L 3 2 CLK2 CLK3 SYSEN_L GNT2_L REQ3_L 2 1 CLK1 GND REQ1_L GNT1_L REQ2_L 1 Table 4 3 J3 User I O Connector ROW A ROW B ROW C ROW D ROW E 19 Reserved 12V 12V RXD3 RXD4 19 18 HSC_EJECT_L GND RXC3 GND RXC4 18 17 HSC_FLOAT MXCLK MXDI MXSYNC_L MXDO 17 16 HSC_GNT_L GND TXC3 GND TXC4 16 15 HSC_REQ_L Reserved ...

Page 77: ... PMCIO36 6 5 PMCIO45 PMCIO44 PMCIO43 PMCIO42 PMCIO41 5 4 PMCIO50 PMCIO49 PMCIO48 PMCIO47 PMCIO46 4 3 PMCIO55 PMCIO54 PMCIO53 PMCIO52 PMCIO51 3 2 PMCIO60 PMCIO59 PMCIO58 PMCIO57 PMCIO56 2 1 VIO PMCIO64 PMCIO63 PMCIO62 PMCIO61 1 Table 4 4 J4 Local PCI Expansion Connector ROW A ROW B ROW C ROW D ROW E 25 AD36 AD35 AD34 AD33 AD32 25 24 AD40 AD39 AD38 GND AD37 24 23 AD45 AD44 AD43 AD42 AD41 23 22 AD49 ...

Page 78: ...V AD12 AD11 AD10 10 9 PAR CBE1 AD15 GND AD14 9 8 STOP 5 0V LOCK PERR SERR 8 7 FRAME IRDY TRDY GND DEVSEL 7 6 AD18 5 0V AD17 AD16 CBE2 6 5 AD21 CLK AD20 GND AD19 5 4 CBE3 5 0V No Connect AD23 AD22 4 3 AD28 AD27 AD26 AD25 AD24 3 2 GNT REQ AD31 AD30 AD29 2 1 INTA INTB INTC INTD RST 1 Table 4 5 J5 User I O Connector ROW A ROW B ROW C ROW D ROW E 22 Reserved GRD Reserved 5V SPKROC_L 22 21 KBDDAT KBDCLK...

Page 79: ... HDSEL_L DSKCHG_L 10 9 MTR1_L DIR_L STEP_L WDATA_L WGATE_L 9 8 RESERVED INDEX_L MTR0_L DS1_L DS0_L 8 7 CS1FX_L CS3FX_L DA1 DASP_L RESERVED 7 6 IOCS16_L GRD PDIAG_L DA0 DA2 6 5 DMARQ IORDY DIOW_L DMACK_L DIOR_L 5 4 DD14 DD0 GND DD15 INTRQ 4 3 DD3 DD12 DD2 DD13 DD1 3 2 DD9 DD5 DD10 DD4 DD11 2 1 RESET_L DRESET_L DD7 DD8 DD6 1 Table 4 6 PCI Mezzanine Card Connector J11 J12 1 TCK 12V 2 1 12V TRST 2 3 G...

Page 80: ...FRAME GND 34 33 GND Not Used 34 35 GND IRDY 36 35 TRDY 3 3V 36 37 DEVSEL 5V 38 37 GND STOP 38 39 GND LOCK 40 39 PERR GND 40 41 SDONE SBO 42 41 3 3V SERR 42 43 PAR GND 44 43 C BE1 GND 44 45 5V AD15 46 45 AD14 AD13 46 47 AD12 AD11 48 47 GND AD10 48 49 AD09 5V 50 49 AD08 3 3V 50 51 GND C BE0 52 51 AD07 Not Used 52 53 AD06 AD05 54 53 3 3V Not Used 54 55 AD04 GND 56 55 Not Used GND 56 57 5V AD03 58 57 ...

Page 81: ... 5V Vio AD56 22 21 PMCIO21 PMCIO22 22 23 AD55 AD54 24 23 PMCIO23 PMCIO24 24 25 AD53 GND 26 25 PMCIO25 PMCIO26 26 27 GND AD52 28 27 PMCIO27 PMCIO28 28 29 AD51 AD50 30 29 PMCIO29 PMCIO30 30 31 AD49 GND 32 31 PMCIO31 PMCIO32 32 33 GND AD48 34 33 PMCIO33 PMCIO34 34 35 AD47 AD46 36 35 PMCIO35 PMCIO36 36 37 AD45 GND 38 37 PMCIO37 PMCIO38 38 39 5V Vio AD44 40 39 PMCIO39 PMCIO40 40 41 AD43 AD42 42 41 PMCI...

Page 82: ...seT 100BaseTX Connector is an RJ45 connector located on the front panel of the MCP750HA SBC The pin assignments for this connector are as follows 57 5V Vio AD32 58 57 PMCIO57 PMCIO58 58 59 Not Used Not Used 60 59 PMCIO59 PMCIO60 60 61 Not Used GND 62 61 PMCIO61 PMCIO62 62 63 GND Not Used 64 63 PMCIO63 PMCIO64 64 Table 4 8 USB 0 Connector J18 1 UVCC0 2 UDATA0N 3 UDATA0P 4 GND Table 4 9 USB 1 Connec...

Page 83: ...M1 signals are also routed to J11 on the transition module A terminal may be connected to J15 or J11 on the transition module but not both at the same time The pin assignments for this connector is as follows Table 4 10 10BaseT 100BaseTX Connector J8 1 TD 2 TD 3 RD 4 AC Terminated 5 AC Terminated 6 RD 7 AC Terminated 8 AC Terminated Table 4 11 COM1 Connector J15 1 DCD 2 RXD 3 TXD 4 DTR 5 GND 6 DSR...

Page 84: ...t will take effect The connector pin out is defined below Debug Connector J16 A 190 pin connector J16 on the MCP750HA base board provides access to the processor bus MPU bus and some bridge memory controller signals It can be used for debugging purposes The pin assignments are listed in the following table Table 4 12 Reset Abort Header J21 1 ABORT_L Active low processor abort 2 GND Ground 3 RESET_...

Page 85: ...0 PD1 40 41 PD2 PD3 42 43 PD4 PD5 44 45 PD6 PD7 46 47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 5V PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 71 PD32 PD33 72 73 PD34 PD35 74 75 PD36 PD37 76 77 PD38 PD39 78 79 PD40 PD41 80 81 PD42 PD43 82 83 PD44 PD45 84 Table 4 13 Debug Connector J16 Continued ...

Page 86: ... PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 No Connection No Connection 112 113 DPE DBDIS 114 115 TT0 TSIZ0 116 117 TT1 TSIZ1 118 119 TT2 TSIZ2 120 121 TT3 No Connection 122 123 TT4 No Connection 124 125 CI No Connection 126 127 WT No Connection 128 129 GLOBAL No Connection 130 131 SHARED DBWO 132 133 AACK 3 3V TS 134 135 ARTY XATS 136 137 DRTY TBST 138 139 TA No Connection 140 141 TEA No Connect...

Page 87: ...STPI 160 161 L2BR CKSTPO 162 163 L2BG HALTED N C 164 165 CLAIM TLBISYNC 166 167 No Connection TBEN 168 169 No Connection No Connection 170 171 No Connection GND No Connection 172 173 No Connection No Connection 174 175 No Connection NAPRUN 176 177 SRST1 QREQ 178 179 SRESET QACK 180 181 HRESET CPUTDO 182 183 GND CPUTDI 184 185 CPUCLK1 CPUTCK 186 187 No Connection CPUTMS 188 189 No Connection CPUTRS...

Page 88: ...llowing table Table 4 14 DRAM Mezzanine Connector J7 1 A_RAS A_CAS 2 3 B_RAS B_CAS 4 5 C_RAS C_CAS 6 7 D_RAS D_CAS 8 9 OEL OEU 10 11 WEL WEU 12 13 ROMACS ROMBCS 14 15 RAMAEN RAMBEN 16 17 RAMCEN EN5VPWR 18 19 RAL0 GND RAL1 20 21 RAL2 RAL3 22 23 RAL4 RAL5 24 25 RAL6 RAL7 26 27 RAL8 RAL9 28 29 RAL10 RAL11 30 31 RAL12 RAU0 32 33 RAU1 RAU2 34 35 RAU3 RAU4 36 37 RAU5 RAU6 38 39 RAU7 RAU8 40 41 RAU9 RAU1...

Page 89: ...L24 RDL25 70 71 RDL26 RDL27 72 73 RDL28 RDL29 74 75 RDL30 RDL31 76 77 RDL32 RDL33 78 79 RDL34 RDL35 80 81 RDL36 RDL37 82 83 RDL38 RDL39 84 85 RDL40 RDL41 86 87 RDL42 RDL43 88 89 RDL44 RDL45 90 91 RDL46 RDL47 92 93 RDL48 RDL49 94 95 RDL50 GND RDL51 96 97 RDL52 RDL53 98 99 RDL54 RDL55 100 101 RDL56 RDL57 102 103 RDL58 RDL59 104 105 RDL60 RDL61 106 107 RDL62 RDL63 108 109 CDL0 CDL1 110 Table 4 14 DRA...

Page 90: ...8 129 RDU10 RDU11 130 131 RDU12 RDU13 132 133 RDU14 3 3V RDU15 134 135 RDU16 RDU17 136 137 RDU18 RDU19 138 139 RDU20 RDU21 140 141 RDU22 RDU23 142 143 RDU24 RDU25 144 145 RDU26 RDU27 146 147 RDU28 RDU29 148 149 RDU30 RDU31 150 151 RDU32 RDU33 152 137 RDU18 RDU19 138 139 RDU20 RDU21 140 141 RDU22 RDU23 142 143 RDU24 RDU25 144 145 RDU26 RDU27 146 147 RDU28 RDU29 148 149 RDU30 RDU31 150 151 RDU32 RDU...

Page 91: ...7 156 157 RDU38 RDU39 158 159 RDU40 RDU41 160 161 RDU42 RDU43 162 163 RDU44 RDU45 164 165 RDU46 RDU47 166 167 RDU48 RDU49 168 169 RDU50 RDU51 170 171 RDU52 GND RDU53 172 173 RDU54 RDU55 174 175 RDU56 RDU57 176 177 RDU58 RDU59 178 179 RDU60 RDU61 180 181 RDU62 RDU63 182 183 CDU0 CDU1 184 185 CDU2 CDU3 186 187 CDU4 CDU5 188 189 CDU6 CDU7 190 Table 4 15 EIDE Compact FLASH Connector J20 1 GND DATA3 2 ...

Page 92: ...TA1 22 23 DATA2 NO CONNECT 24 25 CD2_L CD1_L 26 27 DATA11 DATA12 28 29 DATA13 DATA14 30 31 DATA15 DCS3A_L 32 33 NO CONNECT DIORA_L 34 35 DIOWA_L NO CONNECT 36 37 INTRQA 5V 38 39 MASTER SLAVE NO CONNECT 40 41 RST_L DIORDYA 42 43 NO CONNECT NO CONNECT 44 45 NO CONNECT NO CONNECT 46 47 DATA8 DATA9 48 49 DATA10 GND 50 Table 4 15 EIDE Compact FLASH Connector J20 Continued ...

Page 93: ...vanced user topics For additional information about the PPCBug refer to the PPCBug Firmware Package User s Manual the PPCBug Diagnostics Manual and the CPX750 High Availability PPCBug Firmware User s Manual Each of these manuals is listed in Appendix C Related Documentation PPCBug Basics The PowerPC debug firmware PPCBug is a powerful evaluation and debugging tool for systems built around the Moto...

Page 94: ...ribed in the PPCBug Diagnostics Manual A user interface or debug diagnostics monitor that accepts commands from the system console terminal When using the PPCBug you operate out of either the debugger directory or the diagnostic directory If you are in the debugger directory the debugger prompt PPC1 A Bug is displayed and you have all of the debugger commands at your disposal If you are in the dia...

Page 95: ...ty Where necessary assembly language has been used in the form of separately compiled program modules containing only assembler code No mixed language modules are used Physically PPCBug is contained in two socketed 32 pin PLCC Flash devices that together provide 1MB of storage The executable code is checksummed at every power on or reset firmware entry and the result which includes a precalculated...

Page 96: ...mory from NVRAM 14 Initializes the read write memory controller with the speed of read write memory 15 Retrieves the speed of read only memory Flash from NVRAM 16 Initializes the read only memory controller with the speed of read only memory 17 Enables the MPU s instruction cache 18 Copies the MPU s exception vector table from FFF00000 to 00000000 19 Initializes the PC87307 resources base addresse...

Page 97: ...g message if the verification fails 30 Displays the BUS clock speed verifies that the BUS clock speed matches the configuration data and displays a warning message if the verification fails 31 Displays any Keyboard Controller initialization error that occurs 32 Probes PCI bus for supported network devices 33 Probes PCI bus for supported mass storage devices 34 Initializes the memory IO addresses f...

Page 98: ... GO then control may or may not return to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the System Call Handler routine RETURN described in the PPCBug Firmware Package...

Page 99: ...n list all the available debugger commands by entering the Help HE command alone You can view the syntax description for a particular command by entering HE followed by a space followed by the particular command mnemonic listed below followed by a carriage return Keep in mind that help is now available on both the BUG and DIAG side In addition issuing help on a DIAG test category will give more in...

Page 100: ...U Dump S Records ECHO Echo String ENV Set Environment GD Go Direct Ignore Breakpoints GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable s Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable s Display GN Go to Next Instruction GO Go Execute User Progr...

Page 101: ...m Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot NBH Network Boot Operating System Halt NBO Network Boot Operating System NIOC Network I O Control NIOP Network I O Physical NIOT Network I O Teach Configuration NPING Network Ping OF Offset Registers Display Modify PA Printer Attach NOPA Printer Detach PBOOT Bootstrap Operating System PF Port...

Page 102: ...wer Save Mode RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold Warm Reset RL Read Loop RM Register Modify RS Register Set SD Switch Directories SET Set Time and Date SROM SROM Examine Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display Search T Trace TA Terminal Attach TIME Display Time and Date TM Transparent Mode TT Trace to Tempo...

Page 103: ...tion about the High Availability commands refer to the CPX750 High Availability PPCBug Firmware User s Manual listed in Appendix C Related Documentation Unsupported Commands The following table lists standard PPCBug debugger commands that are not supported on the MCP750HA Table 5 2 High Availability Specific Debugger Commands Name Description PEEPROM Program Verify the HSC EEPROM PCIDOM Initialize...

Page 104: ...s In an active standby arrangement for example the CPU in domain A uses PCIDOM to take control of both the local PCI domain domain A and of the remote domain domain B PWROFF and PWRON allow the user to power off or to power on a module in order to hot swap it Unsupported System Call Interfaces The following table lists standard PPCBug debugger system call interfaces that are not supported on the M...

Page 105: ... High Availability HA features of the CPU module It includes tests for Memory Read Write L2 Cache Real Time Clock Ethernet Controller ISA Bridge Serial Communications Controller UART Keyboard Mouse Controller Parallel Interface PCI PMC Interface EIDE Counter Timer Table 5 5 Unsupported Debugger System Calls Name Description FORKMPU Fork MPU FORKMPUR Fork MPU with Registers IDLEMPU Idle MPU ...

Page 106: ...g displays and all of the debugger and diagnostic commands are available Note that not all tests are valid for the MCP750HA Using the HE command you can list the diagnostic routines available in each test group Refer to the PPCBug Diagnostics Manual listed in Appendix C Related Documentation for complete descriptions of the diagnostic routines and instructions on how to invoke them Table 5 6 Speci...

Page 107: ... Availability features Note that the proper functioning of these commands may depend on specific hardware being installed in the system For further information refer to the CPX750 High Availability PPCBug Firmware User s Manual listed in Appendix C Related Documentation SCC Serial Communications Controller Tests UART Serial Input Output UART Tests VGA543x Video Graphics Tests Z8536 Zilog Z8536 Cou...

Page 108: ...table lists PPCBug diagnostic commands that are part of the standard PPCBug package but are not supported on the MCP750HA system Table 5 8 Unsupported PPCBug Diagnostic Commands Name Description CL1283 Parallel Interface Cirrus CL CD1283 Tests CS4231 CS4231 Audio Codec Tests VGA543X VGA Controller GD543X Tests ...

Page 109: ...C Related Documentation Refer to that manual for general information about their use and capabilities The following paragraphs present additional information about CNFG and ENV that is specific to the PPCBug debugger along with the parameters that can be configured with the ENV command CNFG Configure Board Information Block This command is used to display and configure the Board Information Block ...

Page 110: ...is corrupted Refer to the MCP750 Single Board Computer Programmer s Reference Guide listed in Appendix C Related Documentation for the actual location and other information about the Board Information Block Refer also to the PPCBug Firmware Package User s Manual for a description of CNFG and examples ENV Set Environment Use the ENV command to view and or configure interactively all PPCBug operatio...

Page 111: ...nd is the default mode if NVRAM should fail System mode is defined in the PPCBug Firmware Package User s Manual Y Display the field service menu N Do not display the field service menu Default Y Accesses will be made to the appropriate system buses for example VMEbus local MPU bus to determine the presence of supported controllers Default N Accesses will not be made to the VMEbus to determine the ...

Page 112: ...the SCSI ID value entered here NVRAM Bootlist GEV fw boot path Boot Enable Y N N Y Enable PReP style network booting same boot image from a network interface as from a mass storage device N Do not enable PReP style network booting Default Y SCSI bus is reset on debugger setup N SCSI bus is not reset on debugger setup Default A Asynchronous SCSI bus negotiation Default S Synchronous SCSI bus negoti...

Page 113: ... Default 5 seconds Auto Boot Enable Y N N Auto Boot at power up only Y N N Auto Boot Scan Enable Y N Y Auto Boot Scan Device Type List FDISK CDROM TAPE HDISK Y Give boot priority to devices defined in the fw boot path GEV at power up reset only N Give power up boot priority to devices listed in the fw boot path GEV at any reset Default Y The Autoboot function is enabled N The Autoboot function is ...

Page 114: ...ified in the PowerPC Reference Platform PRP specification If set to zero the firmware will search the partitions in order 1 2 3 4 until it finds the first bootable partition That is then the partition that will be booted Other acceptable values are 1 2 3 or 4 In these four cases the partition specified will be booted without searching Auto Boot Abort Delay 7 The time in seconds that the Autoboot s...

Page 115: ...000 ROM Boot Direct Ending Address FFFFFFFC The last location tested when PPCBug searches for a ROMboot module Default FFFFFFFC Network Auto Boot Enable Y N N Network Auto Boot at power up only Y N N Network Auto Boot Controller LUN 00 Refer to the PPCBug Firmware Package User s Manual listed in Appendix C Related Documentation for a listing of network controller modules currently supported by PPC...

Page 116: ...set might be 1000 but this value is application specific Default 00001000 Caution If you use the NIOT debugger command these parameters need to be saved somewhere in the offset range 00001000 through 000016F7 The NIOT parameters do not exceed 128 bytes in size The setting of this ENV pointer determines their location If you have used the same space for your own program information or commands they...

Page 117: ...ddress is 00000000 Memory Size Ending Address 02000000 The default Ending Address is the calculated size of local memory If the memory start is changed from 00000000 this value will also need to be adjusted DRAM Speed in NANO Seconds 60 The default setting for this parameter will vary depending on the speed of the DRAM memory parts installed on the board The default is set to the slowest speed fou...

Page 118: ...le or burst mode ROM accesses The lowest allowable ROMNAL setting is 0 the highest allowable is F The value to enter depends on processor speed refer to your Processor Memory Mezzanine Module User s Manual for appropriate values The default value varies according to the system s bus clock speed Note ROM Next Access Length is not applicable to the MCP750HA The configured value is ignored by PPCBug ...

Page 119: ...il to come up to a prompt the last code displayed will indicate how far the initialization sequence had progressed before stalling The codes are enabled by an ENV parameter Serial Startup Code LF Enable Y N N A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code This is also enabled by an ENV parameter A list of LED serial codes is included ...

Page 120: ...ds the left most bit matches slot 1 The next bit matches slot 2 This continues through slot 21 which matches the 21st bit Default 00000000 Examples To turn on all of the slots in domain A the contents of the option would be FC000000 Y Domain A will be claimed during board power up and board reset The domain will only be claimed if the other processor board does not already own this domain A non sy...

Page 121: ... are ignored Ignore healthy control word 00000000 Bit oriented word that controls which slots are will have the Ignore Healthy bit set during board power on This word works in conjunction with both domain claiming and with the slot power control word In order to have the Ignore Healthy bit set the following must be true a the domain where the board resides must be claimed b the slot power control ...

Page 122: ...to this command buffer All keystrokes and commands that are valid from the keyboard may be entered into this buffer A user enters the commands as would be done from the keyboard When complete the user enters NULL followed by RETURN The next time the board is power cycled or reset the commands entered into the firmware command buffer will be executed provided it has been enabled Default NULL Exampl...

Page 123: ...Table A 1 MCP750HA Specifications Characteristics Specifications Power requirements Excluding transition module PMC keyboard mouse 5VDC 5 2 8A typical 4 0A max 3 3VDC 5 1 7A typical 2 2A max Operating temperature 5 C to 55 C entry air with forced air cooling refer to Cooling Requirements on page A 2 Storage temperature 40 C to 85 C Relative humidity 5 to 85 non condensing Physical dimensions Base ...

Page 124: ...unters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperature and the type number and location of boards and ...

Page 125: ...ors bonded to a conductive module front panel Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented Failure to do so could compromise the EMC compliance of the equipment containing the module ...

Page 126: ...aration and Installation prior to configuring and installing the TMCP700 Unpacking Instructions Note If the shipping carton is damaged upon receipt request that the carrier s agent be present during the unpacking and inspection of the equipment Unpack the equipment from the shipping carton Carefully check the packing list and verify that all items are present Save the packing material for storing ...

Page 127: ...ace Module modules Two Universal Serial Bus USB ports Two 60 pin Serial Interface Module SIM connectors used for configuring serial ports 3 and 4 A combination keyboard mouse connector A 40 pin header for EIDE port connection A 34 pin header for floppy port connection Two 64 pin headers for PMCIO 1 ground pin provided with each signal A 2 pin header for the speaker Note It is recommened in the ser...

Page 128: ... Connector and Header Locations 2214 9804 COM 1 1 USB 1 SERIAL 4 2 4 1 J1 59 60 J11 1 8 J18 J19 4 1 8 2 7 1 USB 0 J14 J8 2 1 64 63 J21 J9 J13 2 1 1 2 J23 59 60 2 1 64 63 J2 3 1 3 1 2 1 40 39 J15 2 1 34 33 J17 J10 8 2 7 1 J7 17 1 34 18 J24 13 1 26 14 J6 13 1 26 14 COM 2 SERIAL 3 PARALLEL KB MS J16 J3 J5 J4 ...

Page 129: ...l ports Serial Port 3 and 4 are configured through a combination of serial interface module SIM selection and jumper settings The following table lists the SIM connectors and jumper headers corresponding to each of the synchronous serial ports Port 3 is routed to board connector J6 Port 4 is available at board connector J24 Typical interface modules include EIA 232 D DCE and DTE EIA 530 DCE and DT...

Page 130: ...guration of the corresponding SIM module When installing the SIM modules note that the headers are keyed for proper orientation For further information on the preparation of the transition module refer to the TMCP700 Transition Module Installation and Use guide listed in Appendix C Related Documentation The next three figures illustrate the MCP750HA base board and TMCP700 transition module with th...

Page 131: ...llation for TMCP700 B Figure B 2 MCP750HA TMCP700 Serial Ports 1 and 2 DTE Only MCP750HA 2098 9710 4 2 5 7 8 TMCP700 1 3 6 COM1 COM2 4 2 5 7 8 1 3 6 9 1 8 2 6 4 7 3 5 COM1 Front Panel DB9 SOUT1 RTS1 DTR1 SIN1 RI1 CTS1 DSR1 DCD1 PC87307 SOUT2 RTS2 DTR2 SIN2 RI2 CTS2 DSR2 DCD2 J5 ...

Page 132: ...com computer literature B 7 B Figure B 3 TMCP700 Serial Ports 3 and 4 DCE Configuration TMCP700 TXD RTS RXD CTS DCD TRXC RTXC DTR LLB RLB DSR RI TM J3 MX Z85230 SCC Z8536 CIO 3 5 4 2 15 17 24 25 22 21 18 6 7 EIA232 DTE SIM 2097 9709 20 8 MCP750HA J8 J9 3 2 1 ...

Page 133: ...tion and Installation for TMCP700 B Figure B 4 TMCP700 Serial Ports 3 and 4 DTE Configuration TMCP700 TXD RTS RXD CTS DCD TRXC RTXC DTR LLB RLB DSR RI TM J3 MX Z85230 SCC Z8536 CIO 2 4 5 3 24 15 17 18 21 22 25 6 7 EIA232 DTE SIM 2096 9709 8 20 MCP750HA J8 J9 3 2 1 ...

Page 134: ...ition Module may be required to complete the configuration of your particular MCP750HA system If so perform the following steps to install this board For additional information on the TMCP700 Transition Module refer to the TMCP700 Transition Module Installation and Use manual listed in Appendix C Related Documentation 1 Attach an ESD strap to your wrist Attach the other end of the strap to the cha...

Page 135: ...n Module Preparation on page B 1 for instructions on how to do this Caution Avoid touching areas of integrated circuitry static discharge can damage these circuits 4 With the TMCP700 in the rear slot number corresponding to the MCP750HA board carefully slide the transition module into the appropriate slot and seat tightly into the backplane Refer to Figure B 5 for TMCP700 MCP750HA Mating Configura...

Page 136: ... B 11 B Figure B 5 TMCP700 MCP750HA Mating Configuration TMCP700 Transition Module The following tables summarize the pin assignments of connectors that are specific to MCP750HA modules configured for use with TMCP700 transition modules MCP750 TMCP700 J3 J4 J5 J3 J4 J5 ...

Page 137: ...d pins Connector J5 is a 110 pin 2mm hard metric type B connector which routes I O signals for IDE keyboard mouse USB and printer ports The pinout for this connector has been previously described in Table 4 3 on page 4 4 Serial Ports 1 and 2 J10 J11 TMCP700 I O Mode The MCP750HA provides both asynchronous ports 1 and 2 and synchronous asynchronous ports 3 and 4 serial connections The asynchronous ...

Page 138: ...connectors J6 and J24 located on the front panel of the transition module The pin assignments for serial ports 3 and 4 are listed in the following table Table B 2 Serial Connections Ports 3 and 4 J6 and J24 TMCP700 1 No Connection 2 TXDn 3 RXDn 4 RTSn 5 CTSn 6 DSRn 7 GND 8 DCDn 9 SPn_P9 10 SPn_P10 11 SPn_P11 12 SPn_P12 13 SPn_P13 14 SPn_P14 15 TXCIn 16 SPn_P16 17 RXCIn 18 LLBn 19 SPn_P19 20 DTRn 2...

Page 139: ...nts are listed in the following table 23 SPn_P23 24 TXCOn 25 TMn 26 SPn P26 Table B 3 Parallel Connector J7 TMCP700 1 PRBSY GND 19 2 PRSEL GND 20 3 PRACK GND 21 4 PRFAULT GND 22 5 PRPE GND 23 6 PRD0 GND 24 7 PRD1 GND 25 8 PRD2 GND 26 9 PRD3 GND 27 10 PRD4 GND 28 11 PRD5 GND 29 12 PRD6 GND 30 13 PRD7 GND 31 14 PRINIT GND 32 15 PRSTB GND 33 16 SELIN GND 34 17 AUTOFD GND 35 18 Pull up No Connection 3...

Page 140: ...ugged directly into this connector To get keyboard and mouse operations a Y adapter cable is required The pin assignments are listed in the following table USB Connectors J18 J19 Optional TMCP700 I O Mode The TMCP700 has two USB series A receptacles J18 and J19 However the standard version of the MCP700 board does not route the USB signals to these connectors in order to prevent long stubs on the ...

Page 141: ...cs for this connector are listed in the following table Table B 5 EIDE Connector J15 Pin Signal Signal Pin 1 DRESET_L GND 2 3 DD7 DD8 4 5 DD6 DD9 6 7 DD5 DD10 8 9 DD4 DD11 10 11 DD3 DD12 12 13 DD2 DD13 14 15 DD1 DD14 16 17 DD0 DD15 18 19 GND No Connect 20 21 DMARQ GND 22 23 DIOW_L GND 24 25 DIOR_L GND 26 27 IORDY No Connect 28 29 DMACK_L GND 30 31 INTRQ No Connect 32 33 DA1 No Connect 34 35 DA0 DA...

Page 142: ...fboard devices This power is derived from the fused 5VDC power on the MCP750HA Any external device powered from this connector must not draw more than 200mA The pin assignments are listed in the following table Table B 6 Floppy Connector J17 Pin Signal Signal Pin 1 GND No Connect 2 3 GND No Connect 4 5 GND No Connect 6 7 GND Index_L 8 9 GND MTRQ_L 10 11 GND DS1_L 12 13 No Connect DSQ_L 14 15 GND M...

Page 143: ...llowing table PMC I O Connectors J2 J21 The PMC I O connectors consist of two 64 pin header connectors J2 and J21 The pin assignments and signal mnemonics for these connectors are listed in the following two tables Table B 7 5Vdc Power Connector J14 Pin Signal 1 5Vdc 2 GND 3 GND 4 No Connect Table B 8 Speaker Output Connector J13 Pin Signal 1 GND 2 SPKROC_L Table B 9 PMC I O Connector J2 Pin Signa...

Page 144: ...ND PMCIO13 26 27 GND PMCIO14 28 29 GND PMCIO15 30 31 GND PMCIO16 32 33 GND PMCIO17 34 35 GND PMCIO18 36 37 GND PMCIO19 38 39 GND PMCIO20 40 41 GND PMCIO21 42 43 GND PMCIO22 44 45 GND PMCIO23 46 47 GND PMCIO24 48 49 GND PMCIO25 50 51 GND PMCIO26 52 53 GND PMCIO27 54 55 GND PMCIO28 56 57 GND PMCIO29 58 59 GND PMCIO30 60 61 GND PMCIO31 62 63 GND PMCIO32 64 Table B 9 PMC I O Connector J2 Continued Pin...

Page 145: ... PMCIO37 10 11 GND PMCIO38 12 13 GND PMCIO39 14 15 GND PMCIO40 16 17 GND PMCIO41 18 19 GND PMCIO42 20 21 GND PMCIO43 22 23 GND PMCIO44 24 25 GND PMCIO45 26 27 GND PMCIO46 28 29 GND PMCIO47 30 31 GND PMCIO48 32 33 GND PMCIO49 34 35 GND PMCIO50 36 37 GND PMCIO51 38 39 GND PMCIO52 40 41 GND PMCIO53 42 43 GND PMCIO54 44 45 GND PMCIO55 46 47 GND PMCIO56 48 49 GND PMCIO57 50 51 GND PMCIO58 52 53 GND PMC...

Page 146: ...00 Transition Module http www motorola com computer literature B 21 B 57 GND PMCIO61 58 59 GND PMCIO62 60 61 GND PMCIO63 62 63 GND PMCIO64 64 Table B 10 PMC I O Connector J21 Continued Pin Signal Signal Pin ...

Page 147: ...a com computer literature Table C 1 Motorola Computer Group Documents Document Title Publication Number MCP750HA Hot Swap CompactPCI Single Board Computer Installation and Use MCP750HA IH MCP750 Single Board Computer Programmer s Reference Guide MCP750A PG TMCP700 Transition Module Installation and Use TMCP700A IH PPCBug Firmware Package User s Manual Parts 1 and 2 PPCBUGA1 UM PPCBUGA2 UM PPCBug D...

Page 148: ...co com MPC750 D LTC1643L LTC1643H Data Sheet Linear Technology Corporation http www linear tech com LTC1643L LTC1643H MPC750TM RISC Microprocessor User s Manual Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 http merchant hibbertco com mtrlext E mail ldcformotorola hibbertco com MPC750UM AD PowerPCTM Microprocessor Family The Programming Envir...

Page 149: ...KEEPERTM SRAM Data Sheet http us st com stonline index shtml Search for M48T559 SCC Serial Communications Controller User s Manual for Z85230 and other Zilog parts http www zilog com pdfs serial scc_escc_iscc_manual contents html SCC ESCC User s Manual Z8536 CIO Counter Timer and Parallel I O Unit Product Specification and User s Manual in Z8000 Family of Products Data Book http www zilog com prod...

Page 150: ...rtco com OR Morgan Kaufmann Publishers Inc Telephone 415 392 2665 Telephone 1 800 745 7323 http www mkp com books_catalog PowerPC Reference Platform PRP Specification http www ibm com MPR PPC RPU 02 IEEE Standard for Local Area Networks Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications http www ieee org IEEE 802 3 Information Technology ...

Page 151: ...ipment Employing Serial Binary Data Interchange EIA 232 D http www eia org ANSI EIA 232 D Standard Compact PCI Specification http www picmg com CPCI Rev 2 1 Dated 9 2 97 PCI to PCI Bridge Specification PCI ISA Specification http www picmg com Rev 1 02 Rev 2 0 Table C 3 Related Specifications Continued Document Title and Source Publication Number ...

Page 152: ...ition module feature 3 26 Autoboot enable 6 5 B base board layout 1 6 base module feature register 3 18 battery 3 14 for timer 3 14 baud rate power up default 1 18 reconfiguring 1 18 BFL board failure light 3 22 big endian 2 8 board configuration 1 6 board failure LED 3 22 Board Information Block hardware display 6 1 board information block 6 1 6 2 board structure 6 1 built in counters as part of ...

Page 153: ...rresponding to PMC connectors 1 15 control signals support for 3 16 cooling requirements A 2 counters 3 14 CPCI activity LED 3 22 CPU activity LED 3 22 CPU Type register 2 4 CPX750HA relation to MCP750HA 1 1 CTS support for 3 16 D DB9 connector 3 11 B 4 DCD support for 3 16 debug connector J16 4 12 debug firmware PPCBug 5 1 debugger directory 5 14 High Availability System Call Interfaces 5 12 prom...

Page 154: ... 16 Ethernet station address 3 8 Ethernet installed setting for 3 18 Ethernet station address label 3 8 F Falcon ASIC memory controller chip set 2 3 3 25 Falcon ASICs main function 3 25 Falcon memory controller chip set 2 6 2 9 Fast Ethernet 3 8 FCC compliance A 2 feature register base module 3 18 firmware as initialization source 2 1 High Availability commands 5 11 firmware initialization 5 3 fir...

Page 155: ...upt sources 2 6 interrupt support sources 2 6 IRQ3 interrupt request line for COM2 3 10 IRQ4 interrupt request line for COM1 3 10 IRQ7 for parallel port 3 11 ISA bus 2 6 3 11 3 21 as support to M48T559 device 3 14 functions provided 3 3 ISA Super I O functions 3 10 ISASIO 3 10 ISASIO device drives supported 3 11 J J1 as voltage source 1 18 J1 connector 4 2 J10 J11 transition module connectors B 12...

Page 156: ...8T559 Watchdog timer 3 15 manufacturers documents C 2 MCP750 bus capacity 3 3 configuration detail location 3 18 handling big little endian 2 8 MCP750 basic contents 1 1 MCP750HA as source of Flash memory 3 24 configuration information 3 17 debugger console port 1 18 default baud rate 1 18 Ethernet connector 3 8 features hardware 3 1 relation to CPX750HA 1 1 unsupport PPCBug commands 5 11 voltage ...

Page 157: ...s memory map controller 2 4 PHB Device ID 2 4 pin assignments connector xviii 4 1 PMC connectors 3 10 PMC expansion 3 3 PMC function 3 10 PMC I O as transition module feature 3 26 PMC I O connector P2 Adapter B 18 PMC install 1 13 PMC installed setting 3 18 PMC modules as I O expansion options 3 9 PMC Slot as PCI bus master 2 6 PMC slot 3 10 polyswitches fuses 3 23 Port 92 Register as reset source...

Page 158: ...ROM First Access Length 6 9 SCSI Bus Reset on Debugger Startup 6 4 secondary SCSI controller 6 4 Serial Startup Code LF Enable 6 11 Serial Startup Code Master Enable 6 11 PPCBug parameters 6 1 changing 6 1 configurable by ENV 6 3 PPT1 3 11 primary bus 2 5 prompt debugger 5 14 R RAM for timer functions 3 13 RAM300 as source of Flash memory 3 24 RAM300 DRAM installation 1 11 RAM300 memory module 3 2...

Page 159: ...on 3 26 available types 3 26 SNAPHAT battery for real time clock 3 14 SNAPHAT battery location 3 14 software allowed to check chipset 2 4 sources of reset 2 7 speaker output 3 16 function 3 23 specifications base board A 1 startup overview 1 4 status register 3 17 switch abort 3 21 from one PPCBug directory to another 5 6 reset 3 21 sychronous data transfer speed 3 16 synchronous clock signals sup...

Page 160: ... support for 3 16 U UART devices 3 10 uppercase 5 15 using the board 1 4 V VIA 82C586B as PCI bus master 2 5 voltage fuses polyswitches 3 23 W Watchdog timer as part of M48T559 3 15 as reset source 2 7 as type of interrupt 2 6 watchdog timer function 3 13 Watchdog timers as part of Raven 3 15 WDT1 Raven Watchdog timer 3 15 WDT2 Raven Watchdog timer 3 15 Z Z85230 Zilog serial communications interfa...

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Motorola MCP750HA Series, Installation And Use Manual, Page: 101 / 161

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