MC9S12DT256 Device User Guide — V03.07
122
Figure A-9 SPI Slave Timing (CPHA=1)
In Table A-20 the timing characteristics for slave mode are listed.
Table A-20 SPI Slave Mode Timing Characteristics
Num
Characteristic
Symbol
Unit
Min
Typ
Max
1
SCK Frequency
f
sck
DC
—
1
/
4
f
bus
1
SCK Period
t
sck
4
—
t
bus
2
Enable Lead Time
t
lead
4
—
—
t
bus
3
Enable Lag Time
t
lag
4
—
—
t
bus
4
Clock (SCK) High or Low Time
t
wsck
4
—
—
t
bus
5
Data Setup Time (Inputs)
t
su
8
—
—
ns
6
Data Hold Time (Inputs)
t
hi
8
—
—
ns
7
Slave Access Time (time to data active)
t
a
—
—
20
ns
8
Slave MISO Disable Time
t
dis
—
—
22
ns
9
Data Valid after SCK Edge
t
vsck
—
—
30 + t
bus
1
NOTES
:
1. t
bus
added due to internal synchronization delay
ns
10
Data Valid after SS fall
t
vss
—
—
30 + t
bus
ns
11
Data Hold Time (Outputs)
t
ho
20
—
—
ns
12
Rise and Fall Time Inputs
t
rfi
—
—
8
ns
13
Rise and Fall Time Outputs
t
rfo
—
—
8
ns
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5
6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT
SLAVE LSB OUT
BIT 6 . . . 1
4
4
9
12
13
11
(CPOL
=
0)
(CPOL
=
1)
SS
(INPUT)
2
12
13
3
NOTE: Not defined!
SLAVE
7
8
see
note
∞
Summary of Contents for MC9S12A256
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