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5-6

MC92603 Quad Gigabit Ethernet Transceiver Reference Manual

MOTOROLA

Configuration and Control Signals

5.6

Configuration and Control Signals

The MC92603 has many configuration and control signals that are asynchronous to all
input clocks. Most of the signals affect the internal configuration state and must be set at
power up. If the signal’s state is changed after power up, some signals require that the
device be reset by asserting RESET low and then releasing high. Other configuration
signals are meant to be changed during normal operation and do not require a device reset.
However, these signals may still affect device operation. Table 5-3 lists all of the MC92603
asynchronous configuration and control signals and describes the effect of changing their
state after power up.

If MDIO is enabled, then the states may be modified via the MDIO interface. When
MDIO_EN is asserted, the configuration states are loaded on reset as before, and may then
be modified through the interface. The configuration states are read via registers 1, 16, and
17. If any of the hardwired configurations change when MDIO_EN is asserted, the device
must be reset for the action to be initiated. For example, if MDIO_EN is high, changing the
configuration input, XCVR_x_LBE, will be ignored until reset is asserted.

Table 5-3. Asynchronous Configuration and Control Signals

Signal Name

Description

Effect of Changed State

XCVR_x_DISABLE

Transceiver disable

Receiver must acquire new bit phase alignment;
byte and word synchronization must be
re-established.

XCVR_x_LBE

Transceiver loopback enable

Receiver must acquire new bit phase alignment;
byte and word synchronization must be
re-established.

DROP_SYNC

Drop synchronization

Receiver must re-establish byte and word
synchronization.

XMIT_REF_A

Transmitter reference clock A select

Device must be reset

RECV_REF_A

Receiver reference clock A select

Device must be reset

TBIE

Ten-bit interface enable

Device must be reset

HSE

Half-speed enable

Device must be reset

BSYNC

Byte synchronization mode

Device must be reset

ADIE

Add/drop idle enable

Device must be reset

JPAK

Expand receiver FIFO to tolerate Jumbo
packets

Device must be reset

COMPAT

Ethernet compatibility mode

Device must be reset

ENABLE_AN

Enable auto-negotiate

Device must be reset

RCCE

Recovered clock enable

Device must be reset

REPE

Repeater mode enable

Must be low and remain low during normal
operation. Device must be reset if changed.

WSYNC1

Word synchronization enable

Device must be reset

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Summary of Contents for MC92603

Page 1: ...MC92603RM 12 2003 Rev 0 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual Device Supported MC92603VF ...

Page 2: ...he suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applicati...

Page 3: ...rface MDIO Index System Design Considerations Test Features 1 2 3 4 5 6 Glossary of Terms and Abbreviations 8B 10B Coding Scheme Ordering Information Package Description Electrical Specifications and Characteristics Revision History 7 8 A B C GLO IND ...

Page 4: ...rface MDIO Index System Design Considerations Test Features 1 2 3 4 5 6 Glossary of Terms and Abbreviations 8B 10B Coding Scheme Ordering Information Package Description Electrical Specifications and Characteristics Revision History 7 8 A B C GLO IND ...

Page 5: ...tter Interface Signals 2 2 2 3 Transmitter Interface Configuration 2 4 2 3 1 Transmit Driver Operation 2 5 2 3 2 Repeater Mode Operation 2 6 2 4 Backplane Application Modes COMPAT Low 2 6 2 4 1 Transmitting Uncoded Data 8 4 Bit Modes 2 6 2 4 2 Transmitting Coded Data 10 5 Bit Modes 2 8 2 5 Ethernet Compliant Applications Modes COMPAT High 2 9 2 5 1 Transmitting Uncoded Data GMII or RGMII Modes 2 1...

Page 6: ...3 10 3 5 3 1 Word Synchronization Method 3 10 3 6 Receiver Interface Timing Modes 3 12 3 6 1 Recovered Clock Timing Mode RCCE High 3 12 3 6 2 Reference Clock Timing Mode RCCE Low 3 13 3 7 Ethernet Compliant Applications Modes COMPAT High 3 15 3 7 1 Interface to Ethernet MAC 3 15 3 7 1 1 GMII Operation 3 15 3 7 1 2 TBI Operation 3 17 3 7 1 3 Double Data Rate Operation RGMI and RTBI 3 18 3 7 2 Rate ...

Page 7: ...A 16 Vendor Specific Permanent Configuration Control Register 4 9 4 2 10 MDIO RA 17 Vendor Specific Channel Configuration and Status Register 4 11 4 2 11 MDIO RA 18 Vendor Specific BERT Error Counter Register 4 12 Chapter 5 System Design Considerations 5 1 Reference Clock Configuration 5 2 5 2 Startup 5 2 5 3 Standby Mode 5 3 5 4 Receiver Interface Clock Centering 5 3 5 5 Repeater Mode 5 4 5 5 1 T...

Page 8: ... 1 7 1 1 General Parameters 7 1 7 1 2 Absolute Maximum Rating 7 2 7 1 3 Recommended Operating Conditions 7 2 7 2 DC Electrical Specifications 7 3 7 3 AC Electrical Characteristics 7 4 7 3 1 Transmitter Interface Timing 7 4 7 3 1 1 Transmitter Interface Non DDR Timing 7 4 7 3 1 2 Transmitter Interface DDR Timing 7 5 7 3 2 Receiver Interface Timing 7 6 7 3 2 1 Receiver Interface Non DDR Timing 7 7 7...

Page 9: ...f the 256 MAPBGA Package 8 2 8 3 Package Thermal Characteristics 8 5 8 4 MC92603Chip Pinout Listing 8 5 Appendix A Ordering Information Appendix B 8B 10B Coding Scheme B 1 Overview B 1 B 1 1 Naming Transmission Characters B 2 B 1 2 Encoding B 2 B 1 3 Calculating Running Disparity B 3 B 2 Data Tables B 3 Appendix C Revision History Glossary of Terms and Abbreviations Index ...

Page 10: ...Contents Paragraph Number Title Page Number x MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA ...

Page 11: ...r MDIO RA 18 4 12 5 1 PLL Power Supply Filter Circuits 5 7 6 1 Instruction Register 6 2 6 2 Device Identification Register 6 3 7 1 Transmitter Interface Non DDR Timing Diagram 7 4 7 2 Transmitter Interface DDR Timing Diagram 7 5 7 3 Receiver Non DDR Timing Diagram TBIE Low or COMPAT Low 7 7 7 4 Receiver Non DDR Timing Diagram TBIE High and COMPAT High 7 8 7 5 Receiver DDR Timing Diagram TBIE Low o...

Page 12: ...Figures Figure Number Title Page Number xii MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA ...

Page 13: ...nts 3 10 3 7 Receiver Reference Clock is Slower than Transmitter Reference Clock 3 14 3 8 Receiver Reference Clock is Faster than Transmitter Reference Clock 3 14 3 9 GMII Connection to Standard Ethernet MAC 3 15 3 10 Receiver Status in GMII Mode 3 16 3 11 TBI Connection to Standard Ethernet MAC 3 17 3 12 Receiver Interface Error and Status Codes TBI Mode 3 18 3 13 Receiver RGMII Interface 3 18 3 ...

Page 14: ...ransmitter DDR Timing Specifications 7 5 7 6 Target Receiver Clock Offset Relative to Data 7 6 7 7 Receiver Non DDR Timing Specifications TBIE Low or COMPAT Low 7 7 7 8 Receiver Non DDR Timing Specifications TBIE High and COMPAT High 7 8 7 9 Receiver DDR Timing Specification TBIE Low or COMPAT Low 7 9 7 10 Receiver DDR Timing Specification TBIE High and COMPAT High 7 10 7 11 Reference Clock Specif...

Page 15: ...s manual Organization The following is a summary and a brief description of the major chapters in this manual Chapter 1 Introduction gives an overview of the device features and shows a block diagram of the major functional blocks of the part Chapter 2 Transmitter describes the MC92603 transmitter its interfaces and operational options Chapter 3 Receiver gives a description of the receiver its int...

Page 16: ...ormation about the architecture General Information The following documentation published by Morgan Kaufmann Publishers 340 Pine Street Sixth Floor San Francisco CA provides useful information about the PowerPC architecture and computer architecture in general The PowerPC Architecture A Specification for a New Family of RISC Processors Second Edition by International Business Machines Inc Computer...

Page 17: ...oduct The MC92610 3 125 Gbaud Reference Design Platform BR1570 describes the technical design process used in developing a high speed backplane reference design Additional literature is published as new processors become available For a current list of documentation refer to http www motorola com semiconductors Conventions This document uses the following notational conventions Book titles in text...

Page 18: ...xviii MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA ...

Page 19: ...erfaces Each channel also has its own independent MDIO register set as specified in the above standard The MC92603 GEt is designed as four parts in one It may be configured as either a 1 Gigabit backplane serializer deserializer SerDes with functionally similar to the 1 25 Gbaud Quad SerDes MC92600 or as a Quad 1 Gigabit Ethernet PHY and the reduced interface versions of these two The GEt is a hig...

Page 20: ...put interfaces DDR RGMII RTBI source synchronous 4 5 bit optional interfaces Parallel interfaces may be either 2 5 or 3 3 V LVTTL Device will inter operate with SSTL_2 with the 2 5 V LVTTL interface Transmit data clock is selectable between per channel transmit clock or channel A transmit clock Received data may be clocked to the reference clock or to the received data frequencies Unused transceiv...

Page 21: ...s for compatibility with legacy transceivers Selectable COMMA code group alignment mode enables aligned or unaligned transfers Ethernet friendly features GMII TBI RGMII or RTBI data interface options COMMA code group alignment in receivers Provides the PCS and PMA layers for Ethernet PHYs as specified in IEEE Std 802 3 2000 MDIO slave interface and registers as defined in IEEE Std 802 3 2002 are f...

Page 22: ...own in Figure 1 1 and a full block diagram is provided in Figure 1 2 Figure 1 1 MC92603 Simplified Block Diagram XMIT_x_ENABLE XMIT_x_ 7 0 XMIT_x_K ERR XMIT_x_CLK RECV_x_ 7 0 RECV_x_CLK RECV_x_CLK RECV_x_K RECV_x_ERR RECV_x_DV RLINK_x_P RLINK_x_N RESET REF_CLK_P REF_CLK_N GTX_CLK 1 0 MD_DATA MD_CLK CONFIG_INPUTS TDI TRST TCK TDO XCVR_x_DISABLE XCVR_x_LBE MEDIA MD_ENABLE XLINK_x_N XLINK_x_P BIST 8B...

Page 23: ...ESET MDIO Controller MD_DATA MD_ADR 4 2 MD_CLK RECV_B_RCLK RECV_A_RCLK RECV_B_DV XMIT_A_CLK MDIO_EN XMIT_A_ENABLE XMIT_B_ENABLE XMIT_C_ENABLE XMIT_D_ENABLE XCVR_A_LBE XCVR_B_LBE XCVR_C_LBE XCVR_D_LBE GTX_CLK0 GTX_CLK1 TDO RECV_B_COMMA RECV_A_K RECV_A_ERR RECV_A_DV RECV_A_COMMA 8B10B Encoder 8B10B Decoder CLK GEN LINK REF_CLK_P XMIT FIFO RECV FIFO BIST 8B10B Encoder 8B10B Decoder CLK GEN XMIT FIFO ...

Page 24: ... to use the RGMII interfaces to reduce the number of signal traces on the PCB The MC92603 may be used to interface directly to the Gigabit MACs integrated into the MPC PowerQUICC III communications processors They are also interface compatible to C Port s C 3 and C 5 network processors available from Motorola Figure 1 3 PHY and Backplane Applications MC92603 Fiber Backplane MC92603 MC92603 Switch ...

Page 25: ...r 1996 2 Byte Oriented DC Balanced 8B 10B Partitioned Block Transmission Code U S Patent 4 486 739 Dec 4 1984 3 IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std 1149 1 1990 includes IEEE Std 1149 1a 1993 Oct 1993 4 IEEE Standard Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications IEEE Std 802 3 2002 March 2002 ...

Page 26: ...1 8 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA References ...

Page 27: ...cations Modes COMPAT High Section 2 6 Transmitter Redundant Link Operation The MC92603 is a versatile device that may be used in backplane SerDes or Ethernet PHY applications It may be configured in multiple data interface and operational modes The following sections provide a basic functional description of the transmitter its operational modes and data interfaces Each transmitter takes data pres...

Page 28: ... letter x as a place holder for the link identifier letter A through D Internal signals listed in the table are not available at the external interface of the device but are presented to help illustrate the device s operation XMIT Driver XLINK_x_N XLINK_x_P 8B 10B Encoder Serialization Register XMIT_x_ 7 0 XMIT_x_K XMIT FIFO loop_back XMIT Controller BIST Sequence Generator loop_back_data xmit_out...

Page 29: ...isabled Input High XMIT_REF_A Transmit interface clock select Indicates that the transmit interface signals are timed to XMIT_A_CLK instead of individual channel transmit clock Input High LBOE Loopback output enable If LBOE is high link outputs remain active during digital loopback If LBOE is low link outputs are disabled during loopback Input High REPE Repeater mode enable When this input is high...

Page 30: ...etails Input MEDIA Media impedance select Indicates the impedance of the transmission media Low indicates 50 Ω and high indicates 75 Ω Input XLINK_x_N XLINK_x_P Link serial transmit data Differential serial transmit data output pads Output Internal Signals rx_clock High speed transceiver clock Internal differential high speed clock used to transmit and receive link data Input repeat_data Received ...

Page 31: ...he data to be routed with the data ensuring matched delay and timing However if per channel clock sources are not available or deemed unnecessary all channels may be clocked by a common clock source This is enabled by asserting XMIT_REF_A high When XMIT_REF_A is high the XMIT_A_CLK becomes the interface clock for all active channels The configuration settings of the MC92603 affect the legal range ...

Page 32: ...an IDLE K28 5 code group of proper running disparity is generated The states of the XMIT_x_7 XMIT_x_0 XMIT_x_K and XMIT_x_ERR signals are ignored This allows the link partner s receiver to maintain alignment when transmission of data is not needed When XMIT_x_ENABLE is high uncoded data is presented in 8 4 bit bytes to the input register through the XMIT_x_7 XMIT_x_0 signals The uncoded data is co...

Page 33: ... unique 16 code group IDLE K28 5 sequences depending on the current running disparity I I I I I I I I I I I I I I I I or I I I I I I I I I I I I I I I I where I stands for K28 5 of positive disparity and I stands for K28 5 of negative disparity The transmitter inputs XMIT_x_7 XMIT_x_0 XMIT_x_K XMIT_x_ERR and XMIT_x_ENABLE are ignored for the next 15 byte times while this 16 code group sequence is ...

Page 34: ...fficient transition density to ensure reliable clock and data recovery at the receiver If running in the Ethernet TBI or RTBI mode the data will be 8B 10B data NOTE If the code used is not 8B 10B then it must support the K28 5 IDLE code this only applies to backplane mode Ethernet TBI mode is assumed to use 8B 10B The code must be such to guarantee that no two codes when concatenated produce the 8...

Page 35: ...transmitters accept either uncoded data GMII or RGMII interface where the input data is encoded internally by an 8B 10B encoder or coded data TBI or RTBI interface where the input data is pre encoded and the internal encoder is bypassed See Table 2 2 for these interface modes Table 2 7 defines the ordered_sets that are associated with the Gigabit Ethernet protocol Table 2 6 Transmitter Inputs for ...

Page 36: ... at least 10 milliseconds of C1 C2 sequences with all zeros as the Configuration Register contents This forces the remote device to also enter auto negotiate mode The contents of the configuration register are continuously sent until the associated receiver detects the compatible configuration being sent from the link partner The MC92603 is configured as full duplex 1 Gigabit therefore the configu...

Page 37: ...ode group This even odd flag is set at initialization and must be maintained since other events will depend on this even oddness When XMIT_x_ENABLE is raised the data on the XMIT_x_7 through XMIT_x_0 inputs is assumed to be the first byte of an 8 byte preamble The preamble usually consists of 7 consecutive 0x55 code groups followed by a 0xD5 code group The transmitter replaces the first 0x55 code ...

Page 38: ...not affect the transmitter s operation See Section 2 4 2 Transmitting Coded Data 10 5 Bit Modes 2 6 Transmitter Redundant Link Operation The MC92603 is configured as a dual channel SerDes with redundant link input and outputs if the enable redundancy signal ENAB_RED is asserted high Only the data interface to channels A and B will accept data to be transmitted This data will be transmitted over th...

Page 39: ...INK_A_N 1 0 1 Data transmitted over XLINK_C_P XLINK_C_N 1 1 Don t care Data transmitted over XLINK_A_P XLINK_A_N and XLINK_C_P XLINK_C_N Table 2 10 Transmit Channel B Redundant Link Operation ENAB_RED BROADCAST XCVR_B_RSEL Action 0 Don t care Don t care Data transmitted over XLINK_B_P XLINK_B_N 1 0 0 Data transmitted over XLINK_B_P XLINK_B_N 1 0 1 Data transmitted over XLINK_D_P XLINK_D_N 1 1 Don ...

Page 40: ...2 14 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA Transmitter Redundant Link Operation ...

Page 41: ... sections Section 3 1 Receiver Block Diagram Section 3 2 Receiver Interface Signals Section 3 3 Functional Description Section 3 4 Receiver Interface Configuration Section 3 5 Data Alignment Configurations Section 3 6 Receiver Interface Timing Modes Section 3 7 Ethernet Compliant Applications Modes COMPAT High Section 3 8 Backplane Applications Modes COMPAT Low ...

Page 42: ...LINK_x_P RLINK_x_N WSYNC0 WSYNC1 RCCE REPE loop_back_data rx_clock Delay Line Transition Tracking Loop and Data Recovery Comma Detection Byte Alignment HSE BSYNC Word Alignment Alignment FIFO recv_byte_clock Timing Alignment drop add Receiver Interface RECV_x_ERR BIST BERT Analyzer ADIE TBIE TST_0 TST_1 RECV_REF_A DROP_SYNC LBE MEDIA COMPAT repeat_data RECV_x_RCLK JPACK and from PLL RECV_x_DV RECV...

Page 43: ...low see Table 3 10 and Table 3 15 Output RECV_x_RCLK Receiver clock Internally generated clock synchronized with receiver data If TBIE is high then this clock frequency is half of the data frequency Output RECV_x_RCLK_B Receiver clock complement If TBIE is high this is the complement of RECV_x_RCLK If TBIE is low this signal is low Output XCVR_x_DISABLE Transceiver disable When active receiver is ...

Page 44: ...interfaces are to be operated at half speed Input High REPE Repeater mode enable Causes data received to be transmitted over the corresponding transmit channel See Section 5 5 Repeater Mode for details Input High ENAB_RED Enable redundant mode Enable redundant link operation Input High XCVR_x_RSEL Select redundant channel Receive data from secondary redundant channel Input High MEDIA Media impedan...

Page 45: ...chieved when four COMMA code groups with the same alignment are detected NOTE The COMMA code group K28 7 should be used carefully since the combination of this code group with some adjoining code groups will yield false COMMA alignment The receiver also provides for word synchronization this feature is available only in backplane operating modes In this mode all of the receivers are being used coo...

Page 46: ...modulating the duty cycle and period of the received byte clock so that it matches the frequency of the received data see Section 3 6 1 Recovered Clock Timing Mode RCCE High for more information Recovered data is accumulated into 10 bit characters If a byte alignment mode is enabled by asserting BSYNC high the characters are aligned to their original 10 bit boundaries 3 3 3 8B 10B Decoder The 8B 1...

Page 47: ...B_RED will not change states during operation If the state of ENAB_RED is changed then the part must be reset XCVR_A_RSEL and XCVR_B_RSEL inputs may be changed at any time However when the state of this input is changed the channel will lose synchronization and require COMMAs in the data stream to regain alignment 3 4 Receiver Interface Configuration The receiver interface facilitates transfer of ...

Page 48: ...d interface operational modes the receiver signals RECV_x_7 through RECV_x_4 are not used and the 5th and 9th data bits are output on the RECV_x_DV signal With the reduced interface data in the alignment FIFO is presented at the receiver interface as double data rate DDR on the rising and falling edge of the appropriate receiver clock RECV_x_RCLK The receiver status and error reporting is coded on...

Page 49: ...ode groups once locked on an alignment If in the GMII or RGMII mode alignment is acquired per the PCS state diagram as shown in Figure 36 9 of the IEEE Std 802 3 2002 specification 4 Alignment remains locked until any one of three events occur that indicate loss of alignment Alignment is lost when a misaligned COMMA sequence is detected The MC92603 can be configured to automatically realign to a n...

Page 50: ...ernal clock domain DROP_SYNC should be raised prior to XCVR_x_DISABLE is raised and remain high until after XCVR_x_DISABLE is negated low When establishing byte alignment or when data flow is halted due to misalignment the Not Byte Sync error is reported as described in Section 3 7 3 Error Handling 3 5 3 Word Synchronization When the MC92603 is configured in either of the aligned backplane modes B...

Page 51: ...s occur that indicate loss of synchronization Word synchronization lock is lost when one or more of the receivers lose or change byte alignment Byte alignment loss is described in Section 3 5 2 Byte Aligned Mode BSYNC High Lock is also lost when overrun underrun is detected on one or more of the receivers see Section 3 6 2 Reference Clock Timing Mode RCCE Low for more about overrun underrun Finall...

Page 52: ...PLL is not locked All receiver channels data outputs are source synchronous with their respective RECV_x_RCLK outputs They may be configured to be source aligned or source centered with their respective RECV_x_RCLK outputs The configuration signal RECV_CLK_CENT when asserted high will center the receiver clocks relative to the data and status outputs NOTE The receiver clock complement RECV_x_RCLK_...

Page 53: ...s overrun underrun situations Overrun occurs when the link partner s transmitter is running faster than the receiver Underrun occurs when the transmitter is running slower than the receiver To avoid overrun underrun conditions rate adaption performed whereby data is dropped or repeated to allow the data to be presented at the interface at the local reference clock frequency Table 3 7 summarizes th...

Page 54: ... Table 3 12 Table 3 15 or Table 3 16 for a 1 byte clock period and 2 bytes of data are repeated NOTE When operating in word mode both channels must add delete IDLEs simultaneously IDLEs must appear in the data stream for both channels simultaneously so that IDLEs may be repeated or deleted Table 3 7 Receiver Reference Clock is Slower than Transmitter Reference Clock ADIE COMPAT Receive Mode Result...

Page 55: ...C92603 Port Name GTX_CLK Transmit clock Input XMIT_x_CLK TX_EN Transmit enable Input XMIT_x_ENABLE TX_ER Force error on transmitted byte Input XMIT_x_ERR TXD 7 0 Transmit data Input XMIT_x_7 0 RX_CLK Receive clock Output RECV_x_RCLK RXD 7 0 Receive data Output RECV_x_ 7 0 RX_ER Receiver has detected an error Output RECV_x_ERR RX_DV Receiver has detected data Output RECV_x_DV CRS Receiver has sense...

Page 56: ...aised This is per Figures 36 7a and 36 7b of IEEE Std 802 3 2002 specification 4 Data continues to be presented on the data outputs and the RECV_x_DV output remains high until an End_of_Packet code group T is received At this point the RECV_x_DV output is negated low and remains low until the next Start_of_Packet is received When operating in GMII mode the receiver status is reported by RECV_x_ERR...

Page 57: ... not realign to any future COMMAs that may appear in the data stream If enable COMMA detect is enabled XMIT_x_K is high a data code group may be repeated to force this alignment if an IDLE is encountered in an ODD code group Table 3 11 TBI Connection to Standard Ethernet MAC IEEE Std 802 3 2002 Signal Name Function Direction Relative to MC92603 Port Name PMA_TX_CLK Transmit clock Input XMIT_x_CLK ...

Page 58: ... error codes are not valid 10 bit encoded data RECV_x_ COMMA RECV_x_ ERR RECV_x_ DV RECV_x_ 7 0 Priority2 2 The priority column shows the error that is reported if multiple errors occur at the same time The lower numbered priority errors are reported first Description Low Low Data 9 Data 8 Data 7 0 6 Normal operation non COMMA code group received Low High Data 9 Data 8 Data 7 0 5 Normal operation ...

Page 59: ...patibility mode Context sensitive rate adaption during receipt of configuration IDLE and data code groups Tolerates up to 100 ppm frequency offset Supports Jumbo frame lengths of up to 14 Kbytes if JPACK is high Supports frame bursting Internal or external 8B 10B encoding decoding may be used Compatible with IEEE Std 802 3 2002 Clause 4 specification 4 of media access control function Compatible w...

Page 60: ...an imminent underflow searches for two adjacent C1 C2 code group sets with a constant configuration register value and inserts a copy of them into the packet stream adding a total of 16 code groups The auto negotiation function is tolerant of additional valid sets because of its handshaking protocol In order to maintain proper running disparity as described above two complete C1 C2 code group sets...

Page 61: ...to code group packets The code groups in the packet cannot be disturbed therefore rate adaption is accomplished in the IPG as described above On detection of an imminent overflow the MC92603 searches for and deletes an I2 ordered set removing a total of two or four code groups from the IPG On detection of an imminent underflow the MC92603 searches for a I2 ordered set and inserts an I2 adjacent to...

Page 62: ...2603 transmit controller to shorten the IPG by two to achieve even odd alignment and for the receiver to remove four code groups in the IPG to perform rate adaption if in reference clock mode This means that if the IPG is only 12 code groups originally then the receiver could present an IPG as small as 6 code groups with maximum frequency offset If at least eight code groups are required in the IP...

Page 63: ...RECV_x_ ERR RECV_x_ DV RECV_x_K RECV_x_ COMMA RECV_x_ 7 0 Priority 1 1 The priority column shows the error that is reported if multiple errors occur at the same time The lower priority numbered errors are reported first Description Low Low Don t care Don t care Don t care Undefined for backplane byte mode Low High Low Don t care Data 9 Normal operation valid data code group received Low High High ...

Page 64: ...V_x_ 7 0 Priority 1 1 The priority column shows the error that is reported if multiple errors occur at the same time The lower priority numbered errors are reported first Description Low Low Data 9 Data 8 Data 7 0 6 Normal operation non COMMA code group received Low High Data 9 Data 8 Data 7 0 5 Normal operation COMMA K28 1 K28 5 or K28 7 code group received High Don t care Don t care Don t care 0...

Page 65: ...Some users may wish to use the MDIO interface and others may not If the MDIO interface is to be used then the MDIO enable input MDIO_EN must be asserted high The MDIO interface is available whether COMPAT is enabled or not On power up the MC92603 will always assume the default configuration defined by the pins of the device The configuration can then be changed through the MDIO interface regardles...

Page 66: ...and are considered part of the extended register set The MC92603 has four sets of MDIO registers one per transceiver channel Registers for address 0 6 and 15 18 as defined in the standard specification are fully supported Registers 7 14 and 19 31 are not supported in the MC92603 The MDIO registers are identified in Table 4 1 Table 4 1 MDIO Management Register Set MDIO Register Address RA Register ...

Page 67: ...el is in loopback mode data transmitted into the transmit interface is looped back on the serial link input to the same channel s receiver R W 13 Speed select 0 Bit 13 is forced to zero and may not be modified MC92603 is always configured as a 1 gigabit device R 12 Auto negotiation enable Bit 12 is initialized to the value on the ENABLE_AN input but may be modified through the MDIO interface R W 1...

Page 68: ... modified MC92603 does not support 100BASE X operation R 13 100BASE X half duplex Bit 13 is forced to zero and may not be modified MC92603 does not support 100BASE X operation R 12 10 Mb s full duplex Bit 12 is forced to zero and may not be modified MC92603 does not support 100BASE 10 Mb s operation R 11 10 Mb s half duplex Bit 11 is forced to zero and may not be modified MC92603 does not support ...

Page 69: ...y be changed via register 0 12 through the MDIO interface R 2 Link status Bit 2 is initialized to zero It reflects whether the receiver has achieved byte synchronization R 1 Jabber detect Bit 1 is forced to zero and may not be modified R 0 Extended capability Bit 0 is forced to one and may not be modified The MC92603 has a specific status and configuration register register 17 for each channel R 1...

Page 70: ...gure 4 4 Auto Negotiation AN Advertisement Register MDIO RA 4 Table 4 4 AN Advertisement Register MDIO RA 4 Field Descriptions Bits Name Description 1 1 R read only R W read and write 15 Next page Forced to zero The MC92603 does not support multiple pages of configuration registers R 14 Acknowledge Ack is set when the receiver detects a valid configuration from the link partner s transmitter R 13 ...

Page 71: ...Table 4 5 AN Link Partner Ability Register Field Descriptions Bits Name Description 1 1 R read only 15 Next Page The MC92603 does not support multiple pages of configuration registers and ignores this bit R 14 Acknowledge Ack is set when the link partner acknowledges receipt of the advertised transmitted capabilities R 13 Remote fault 2 Bits 13 and 12 are the remote status of the link partner R RF...

Page 72: ...Register Figure 4 7 shows the content of the extended status register MDIO RA 15 and its state for the MC92603 The register is read only and may not be modified The MC92603 only supports 1000BASE X full duplex operation Therefore bit 15 is forced to a one and bits 14 12 are forced to zeros 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Next Page Enable Page Received Reserved W Reset 0 0 0 0 0 0 ...

Page 73: ...ref_a tbie bsync compat rcce repe wsync1 W Reset XMIT_REF_A RECV_REF_A TBIE BSYNC COMPAT RCCE REPE WSYNC1 7 6 5 4 3 2 1 0 R wsync0 jpack adie tst_1 tst_0 lboe use_short_ an_timer ddr W Reset WSYNC0 JPACK ADIE TST_1 TST_0 LBOE 0 DDR Figure 4 8 Permanent Configuration Control Register MDIO RA 16 Table 4 6 Permanent Configuration Control Register Field Descriptions Bits Name Description 1 15 xmit_ref...

Page 74: ...k_reg Initialized to the value on the jpack input If set allows jumbo packets of data to be received lengthens the receive FIFO See Section 3 7 2 4 Data Context for details R W 5 adie_reg Initialized to the value on the ADIE input If receivers are set to reference clock mode rcce_reg 0 setting adie_reg allows code groups to be inserted deleted to prevent overrun underrun See Section 3 6 2 Referenc...

Page 75: ...o May be written through the MDIO interface A software disable when set indicates that channel is to be disabled to reduce power The channel is disabled if either bit 15 or 14 are set R W 14 i_xcvr_x_disable Contains the value of the XCVR_x_DISABLE input R 13 overrun Bit 13 is initialized to zero and then is set to one only if this channel overruns due to clock mismatch between the transmitter and...

Page 76: ...face If set indicates that data will be transmitted received over the secondary redundant links Only applicable to Channel A and B R W 7 0 recv_error_ctr Initialized to zero This 8 bit counter is incremented whenever this channel s receiver detects a code error or disparity error This counter is cleared when read through the MDIO interface This counter cannot be loaded other than cleared through t...

Page 77: ...on 5 5 Repeater Mode Section 5 6 Configuration and Control Signals Section 5 7 Power Supply Requirements Section 5 8 Phase Locked Loop PLL Power Supply Filtering Section 5 9 Power Supply Decoupling Recommendations This chapter describes general system considerations for the MC92603 Quad Gigabit Ethernet transceiver including the following Device startup Initialization and proper use of the configu...

Page 78: ...CLK_N are used as the clock source If USE_DIFF_CLOCK is low the TTL_REF_CLK input is used as the clock source The differential reference clock inputs REF_CLK_P N may also be driven by a single ended source The REF_CLK_N input must be set at VREF 1 25 V for a single ended operation of REF_CLK_P and must be connected to its own reference voltage circuit When using the differential LVPECL inputs the ...

Page 79: ...ed 5 4 Receiver Interface Clock Centering All interface output drivers are internally source terminated with 50 Ω Therefore no external source terminations are required The receiver interface also has the option of having the output data source aligned or source centered with the respective channel RECV_x_CLK If source aligned then the considerations for pcb design must include lengthening the clo...

Page 80: ... serial links This mode does not attempt to meet the standard for Ethernet repeaters as defined in Clause 41 of IEEE Std 802 3 2002 4 5 5 1 Ten Bit Interface Mode When the device is in 10 bit interface mode TBIE high the internal 8B 10B encoder and decoder are bypassed and the 10 bit data received is forwarded directly to the transmitter Running disparity is assumed correct and is not checked When...

Page 81: ...92603 s four transmitters are timed exclusively to the reference clock domain therefore the recovered clock mode cannot be used in repeater mode The setting on the recovered clock enable input RCCE is ignored when in repeater mode and all data is timed to the reference clock 5 5 5 Add Drop Idle Mode Repeater mode is timed exclusively to the reference clock domain as stated above A frequency offset...

Page 82: ...et for the action to be initiated For example if MDIO_EN is high changing the configuration input XCVR_x_LBE will be ignored until reset is asserted Table 5 3 Asynchronous Configuration and Control Signals Signal Name Description Effect of Changed State XCVR_x_DISABLE Transceiver disable Receiver must acquire new bit phase alignment byte and word synchronization must be re established XCVR_x_LBE T...

Page 83: ...round connection should be near the PLLAGND ball The 0 01 µF capacitor is closest to the ball followed by the 1 µF capacitor and finally the 1 Ω resistor to VDD on the 1 8 V power plane The capacitors are connected from PLLAGND to the ground plane Ceramic chip capacitors with the highest possible self resonant frequency should be used All traces should be kept short wide and direct Figure 5 1 PLL ...

Page 84: ...V VDD and XVDD balls of the device The board should also have about 10 10 nF SMT ceramic chip capacitors as close as possible to the VDDQ balls of the device Where the board has blind vias these capacitors should be placed directly below the MC92603 supply and ground connections Where the board does not have blind vias these capacitors should be placed in a ring around the MC92603 as close to the ...

Page 85: ...vers the JTAG implementation and the system accessible test modes 6 1 IEEE Std 1149 1 Implementation This section describes the IEEE Std 1149 1 compliant test access port and boundary scan architecture implementation in the MC92603 6 1 1 Test Access Port TAP Interface Signals Table 6 1 lists the interface signals for the TAP Table 6 1 TAP Interface Signals Signal Name Description Function Directio...

Page 86: ...es a reset after power up Connect TRST to RESET Terminate TRST with a 1 KΩ resistor or hardwire to ground 6 1 2 Instruction Register Figure 6 1 shows the format for the instruction register Figure 6 1 Instruction Register 6 1 3 Instructions Table 6 2 lists the public instructions provided in the implementation and their instruction codes Bit Position 3 2 1 0 Field IR Capture IR Value 0 0 0 1 Table...

Page 87: ...n Register 0x0281E01D Figure 6 2 shows the format for the device identification register All bits of the register are read only 6 1 6 Performance The performance and electrical properties of the TAP controller boundary scan and JTAG inputs and outputs are described in Chapter 7 Electrical Specifications and Characteristics Table 6 3 Tap Controller Private Instruction Codes Instruction Code Instruc...

Page 88: ...ill function normally When in loopback mode the XLINK_x_P and XLINK_x_N output signals will continue to operate normally The receiver s link input signals RLINK_x_P and RLINK_x_N are electrically isolated during loopback mode such that their state does not affect the loopback path LBOE controls the state of the XLINK_x_P XLINK_x_N output signals during loopback testing If LBOE is low XLINK_x_P XLI...

Page 89: ...OTE An error counter is maintained in MDIO RA 18 for each specific channel in all BIST test modes See Chapter 4 Management Interface MDIO for details The RECV_x_ERR RECV_x_DV and RECV_x_COMMA signals as interpreted and shown in Table 6 5 have special meaning in this test mode They report the status of the receiver and PN analysis logic The BIST sequence makes use of the 8B 10B encoder decoder Ther...

Page 90: ...er as described above The transmitter will automatically go through sequences 2 and 3 on entering this test mode When testing is complete the device will need to be reset before normal operation can resume If IDLEs are to be inserted TST_1 low TST_0 high XCVR_A_LBE high then IDLEs K28 5 code group are inserted every 2048 code groups during sequence 3 If COMPAT is high I1 I2 code groups will be ins...

Page 91: ...n 7 2 DC Electrical Specifications Section 7 3 AC Electrical Characteristics 7 1 General Characteristics This section provides the general parameters absolute maximum ratings and recommended operating conditions for the MC92603 7 1 1 General Parameters A summary of the general parameters for the MC92603 are as follows Package 256 MAPBGA 17 x 17 mm body size 1 mm ball pitch Core power supply 1 8 V ...

Page 92: ...ply voltage XVDD 0 3 2 2 V LVCMOS TTL input voltage Vin 0 3 VDDQ 0 3 V Link input voltage Vin 0 3 XVDD 0 3 V Storage temperature range Tstg 55 150 C ESD tolerance HBM 2000 V MM 200 V Table 7 2 Recommended Operating Conditions Characteristic 1 2 1 These are the recommended and tested operating conditions Proper device operation outside of these conditions is not guaranteed 2 Recommended supply powe...

Page 93: ...OS TTL input low voltage VIL 0 3 0 7 V LVCMOS TTL input leakage current Vin VDDQ IIH 10 µA LVCMOS TTL input leakage current Vin GND IIL 10 µA LVCMOS TTL output high voltage IOH 7 6 mA VOH 1 76 V LVCMOS TTL output low voltage IOL 7 6 mA VOL 0 54 V LVCMOS TTL output high voltage IOH 2 mA VOH 2 0 V LVCMOS TTL output low voltage IOL 2mA VOL 0 4 V LVCMOS TTL input capacitance Cin 10 pF LVCMOS TTL outpu...

Page 94: ...nterface mode timing is non double data rate non DDR the input data is sampled and stored on the rising edge of the transmit interface clock XMIT_x_CLK When operating in the reduced 4 or 5 bit backplane or RGMII RTBI Ethernet modes the interface is double data rate DDR and the data is sampled and stored on both the rising and falling edges of the transmit interface clock XMIT_x_CLK The following t...

Page 95: ...of XMIT_x_CLK 0 0 1 1 Synchronous to channel s transmit interface clock XMIT_REF_A low ns GMII or TBI 0 200 1 ns Backplane modes 0 600 2 2 Synchronous to XMIT_A_CLK XMIT_REF_A high ns All modes Φdrift Phase drift between XMIT_x_CLK and REF_CLK 180 180 degrees All modes Table 7 5 Transmitter DDR Timing Specifications Symbol Characteristic Min Max Unit Application Mode T1 Setup time prior to rising ...

Page 96: ...t of the clock edge with respect to the data depending on the device application configuration Note that the complement of the receiver clock RECV_x_RCLK_B is only valid and available in TBI and RTBI Ethernet compliant applications modes Table 7 6 also lists references to timing figures in the following receiver interface timing sections Table 7 6 Target Receiver Clock Offset Relative to Data Appl...

Page 97: ...T Low Table 7 7 provides the receiver non DDR timing specifications when TBIE is negated low or COMPAT is negated low Table 7 7 Receiver Non DDR Timing Specifications TBIE Low or COMPAT Low Symbol Characteristic 1 1 10 pF output load Aligned Clock Centered Clock Unit Note Min Max Min Max T1 Output valid time before rising edge of RECV_x_RCLK 0 500 0 500 3 500 ns 2 2 Full speed HSE low 1 000 1 000 ...

Page 98: ...ng Specifications TBIE High and COMPAT High Symbol Characteristic 1 1 10 pF output load Aligned Clock Centered Clock Unit Note Min Max Min Max T1 Output valid time before rising edge of RECV_x_RCLK or RECV_x_RCLK_B 0 500 0 500 3 500 ns 2 2 Full speed HSE low 1 000 1 000 7 500 ns 3 3 Half speed HSE high T2 Output valid time after rising edge of RECV_x_RCLK or RECV_x_RCLK_B 7 000 3 500 ns 2 15 000 7...

Page 99: ...cations when TBIE is negated low or COMPAT is negated low Table 7 9 Receiver DDR Timing Specification TBIE Low or COMPAT Low Symbol Characteristic 1 1 10 pF output load Aligned Clock Centered Clock Unit Note Min Max Min Max T1 Output valid time before rising falling edge of RECV_x_RCLK 0 500 0 500 1 440 ns 2 2 Full speed HSE low 1 000 1 000 3 440 ns 3 3 Half speed HSE high T2 Output valid time aft...

Page 100: ... 10 pF output load Aligned Clock Centered Clock Unit Note Min Max Min Max T1 Output valid time before rising edge of RECV_x_RCLK or RECV_x_RCLK_B 0 500 0 500 1 440 ns 2 2 Full speed HSE low 1 000 1 000 3 440 ns 3 3 Half speed HSE high T2 Output valid time after rising edge of RECV_x_RCLK or RECV_x_RCLK_B 3 000 1 420 ns 2 7 000 3 420 ns 3 T3 RECV_x_RCLK or RECV_x_RCLK_B cycle time 15 800 16 200 15 ...

Page 101: ..._P N rise time 1 1 Measured between 10 90 percent points 2 0 ns Tf REF_CLK_P N fall time 1 2 0 ns frange REF_CLK_P N frequency range 2 3 2 Measured between 50 50 percent points 3 Full speed operation HSE low 95 135 MHz frange REF_CLK_P N frequency range 2 4 4 Half speed operation HSE high 47 5 67 5 MHz TD REF_CLK_P N duty cycle 45 55 Tdiff REF_CLK_P to REF_CLK_N differential skew 1 0 ns ftol REF_C...

Page 102: ...rcent points 0 24 UI Tdj Deterministic jitter 1 0 12 UI Tds Differential skew 1 25 ps Xla Transmit latency 2 2 Rising edge XMIT_x_CLK to bit 0 transmit 57 bit times Table 7 13 Link Differential Input Timing Specifications Symbol Characteristic Min Max Unit Tr Link input rise time 1 1 Measured between 10 90 percent points 300 ps Tf Link input fall time 1 300 ps Tjtol Total jitter tolerance 2 3 2 Me...

Page 103: ...ace timing diagram Figure 7 10 MDIO Interface Timing Diagram Table 7 14 provides the MDIO interface timing specifications Table 7 14 MDIO Interface Timing Specifications Symbol Characteristic Min Max Unit T1 Setup time prior to rising edge of MD_CLK 10 ns T2 Hold time after rising edge of MD_CLK 10 ns T3 MD_CLK period 100 ns T4 Turnaround delay time MD_DATA sourced by PHY 1 1 Load 470 pF 25 ns T1 ...

Page 104: ...ure 7 11 JTAG I O Timing Diagram Table 7 15 provides the JTAG I O timing specifications Table 7 15 JTAG I O Timing Specifications Symbol Characteristic Min Max Unit T1 Output propagation time after falling edge of TCK 1 1 10 pF output load 1 0 8 0 ns T2 Setup time to rising edge of TCK 1 0 ns T3 Hold time to rising edge of TCK 0 5 ns fTCK TCK frequency 20 MHz TD TCK duty cycle 35 65 tr tf TCK inpu...

Page 105: ...The following section provides the package parameters and mechanical dimensions of the MC92603device The MC92603 is offered in a 256 MAPBGA package The 256 MAPBGA utilizes an aggressive 1 mm ball pitch and 17 mm body size for applications where board space is limited 8 1 256 MAPBGA Package Parameter Summary Package Type Fine pitch ball grid array Package Outline 17 mm x 17 mm Package Height 1 60 m...

Page 106: ...g of the 256 MAPBGA package Figure 8 2 provides the package dimensions Figure 8 3 provides a graphic of the package pin signal mappings Figure 8 1 256 MAPBGA Nomenclature X E D Y LASER MARK FOR PIN A1 TOP VIEW DETAIL K M M VIEW M M BOTTOM VIEW S 15X e 0 20 SHEET 2 OF 2 4X P N M L K J H G F E D C B A R T 12 11 10 6 5 4 3 2 1 9 13 14 7 8 15 16 3 0 25 0 10 Z X Y Z 256X b M M METALIZED MARK FOR PIN A1...

Page 107: ...SIONS AND TOLERANCES PER ASME Y14 5M 1994 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z DATUM Z SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE 5 4 3 2 1 1 25 0 27 0 40 1 16 REF 17 00 BSC 17 00 BSC 1 00 BSC 0 50 BSC DETAIL K A A1 Z 4 VIEW ROTATED 90 CLOCKW...

Page 108: ... RCLK_B RECV_B_ COMMA RECV_ B_DV XLINK_ B_P XLINK_ B_N RECV_ CLK_CENT XMIT_ C_CLK XMIT_ C_0 XMIT_ C_1 XMIT_ C_2 XMIT_ C_3 XMIT_ C_4 XMIT_ C_5 XMIT_ C_6 XMIT_ C_7 XMIT_ C_K XCVR_C_ DISABLE XMIT_ C_ERR XMIT_C_ ENABLE RECV_ C_3 RECV_ C_4 RECV_ C_7 RECV_ C_K RECV_ C_ERR RECV_C_ COMMA RECV_ C_DV RECV_ C_RCLK RECV_C_ RCLK_B XMIT_ D_CLK XMIT_ D_0 XMIT_ D_5 XMIT_ D_K XMIT_ D_7 XMIT_ D_2 XMIT_ D_6 XMIT_ D_...

Page 109: ...junction to ambient 200 LFM 1 1 Air flow in linear feet per minute 29 θja 4 Thermal resistance from junction to ambient 400 LFM1 27 Table 8 2 MC92603 Signal to Ball Mapping Signal Name Description Ball Number 256 MAPBGA Direction I O Type XMIT_A_CLK Transmitter A Interface Clock T9 Input LVTTL XMIT_A_0 Transmitter A Data bit 0 T8 Input LVTTL XMIT_A_1 Transmitter A Data bit 1 R8 Input LVTTL XMIT_A_...

Page 110: ...T_B_1 Transmitter B Data bit 1 A8 Input LVTTL XMIT_B_2 Transmitter B Data bit 2 A9 Input LVTTL XMIT_B_3 Transmitter B Data bit 3 B9 Input LVTTL XMIT_B_4 Transmitter B Data bit 4 C9 Input LVTTL XMIT_B_5 Transmitter B Data bit 5 D9 Input LVTTL XMIT_B_6 Transmitter B Data bit 6 E9 Input LVTTL XMIT_B_7 Transmitter B Data bit 7 A10 Input LVTTL XMIT_B_K Transmitter B K A11 Input LVTTL XMIT_B_ERR Transmi...

Page 111: ...MIT_C_ENABLE Transmitter C Enable Data In D7 Input LVTTL XCVR_C_DISABLE Transceiver C Disable E7 Input LVTTL RECV_C_0 Receiver C Data bit 0 D1 Output LVTTL RECV_C_1 Receiver C Data bit 1 E2 Output LVTTL RECV_C_2 Receiver C Data bit 2 G5 Output LVTTL RECV_C_3 Receiver C Data bit 3 F3 Output LVTTL RECV_C_4 Receiver C Data bit 4 E1 Output LVTTL RECV_C_5 Receiver C Data bit 5 F2 Output LVTTL RECV_C_6 ...

Page 112: ...D_6 Receiver D Data bit 6 F5 Output LVTTL RECV_D_7 Receiver D Data bit 7 C2 Output LVTTL RECV_D_COMMA Receiver D COMMA Detect status B4 Output LVTTL RECV_D_K Receiver D K status D6 Output LVTTL RECV_D_DV Receiver D Data Valid status C5 Output LVTTL RECV_D_ERR Receiver D Error Detect A4 Output LVTTL RECV_D_RCLK Receiver D Receive Data Clock C3 Output LVTTL RECV_D_RCLK_B Receiver D Data Clock Comple...

Page 113: ...L LBOE Loopback Output Enable R12 Input LVTTL STNDBY Standby Mode Enable P14 Input LVTTL MEDIA Media Impedance Select N9 Input LVTTL RECV_CLK_CENT Center Recov Clock Relative to Data A12 Input LVTTL JPACK Enable Jumbo Packets T10 Input LVTTL WSYNC1 Word Sync Definer M12 Input LVTTL WSYNC0 Word Sync Definer P13 Input LVTTL TMS JTAG Test Mode Select B12 Input LVTTL TDI JTAG Test Data In A13 Input LV...

Page 114: ...L CMOS I O Supply 10 F6 7 F10 11 J6 J11 K6 K11 L8 9 VDDQ Supply XVDD Link I O Supply 5 F15 G15 J14 M15 N15 XVDD Supply XGND Link I O Ground 5 F16 H14 J13 L14 M16 GND Ground XVDDC Core Analog Logic Supply 6 C15 D15 G12 J12 K12 L15 XVDD Supply XGNDC Core Analog Ground 2 H12 L12 GND Ground V SHIELD Link VDD Shield 4 F13 H15 N13 P15 XVDD Supply G SHIELD Link Ground Shield 4 C16 E15 J16 K13 GND Ground ...

Page 115: ...ing nomenclature for the MC92603 Quad Gigabit Ethernet transceiver For product availability contact your local Motorola Semiconductor sales representative Figure A 1 Motorola Part Number Key M C 9 2 6 0 3 V F Product Code Part Identifier Package VF 256 pin MAPBGA Product Revision MC Production Product XC Pilot Production ...

Page 116: ...A 2 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA ...

Page 117: ...sures proper DC balance across the link and is sufficient for good clock recovery In the 8B 10B notation scheme bytes are referred to as transmission characters and each bit is represented by letters Unencoded bits the 8 bits that have not passed through a 8B 10B encoder are represented by letters A through H which are bits 0 through7 Figure B 1 Unencoded Transmission Character Bit Ordering Encode...

Page 118: ...e bits The letters H G and F comprise the 3 bit block and the letters E D C B and A comprise the 5 bit block 3 The 3 bit and 5 bit sub blocks pass through a 3B 4B encoder and a 5B 6B encoder respectively A bit is added to each sub block such that the transmission character is encoded and expanded to a total of 10 bits 4 At the time the character is expanded into 10 bits it is also encoded into the...

Page 119: ...lock is positive if 1 the encoded sub block contains more 1s than 0s 2 if the 6 bit sub block is 6 b00 0111 or 3 if the 4 bit sub block is 4 b0011 Running disparity at the end of any sub block is negative if 1 the encoded sub block contains more 0 than 1 bits 2 if the 6 bit sub block is 6 b11 1000 or 3 if the 4 bit sub block is 4 b1100 Otherwise running disparity at the end of the sub block is the...

Page 120: ...1 101100 1011 101100 0100 D13 1 001 01101 101100 1001 101100 1001 D14 0 000 01110 011100 1011 011100 0100 D14 1 001 01110 011100 1001 011100 1001 D15 0 000 01111 010111 0100 101000 1011 D15 1 001 01111 010111 1001 101000 1001 D16 0 000 10000 011011 0100 100100 1011 D16 1 001 10000 011011 1001 100100 1001 D17 0 000 10001 100011 1011 100011 0100 D17 1 001 10001 100011 1001 100011 1001 D18 0 000 1001...

Page 121: ...0111 0011 101000 1100 D16 2 010 10000 011011 0101 100100 0101 D16 3 011 10000 011011 0011 100100 1100 D17 2 010 10001 100011 0101 100011 0101 D17 3 011 10001 100011 1100 100011 0011 D18 2 010 10010 010011 0101 010011 0101 D18 3 011 10010 010011 1100 010011 0011 D19 2 010 10011 110010 0101 110010 0101 D19 3 011 10011 110010 1100 110010 0011 D20 2 010 10100 001011 0101 001011 0101 D20 3 011 10100 00...

Page 122: ... 101 01111 010111 1010 101000 1010 D16 4 100 10000 011011 0010 100100 1101 D16 5 101 10000 011011 1010 100100 1010 D17 4 100 10001 100011 1101 100011 0010 D17 5 101 10001 100011 1010 100011 1010 D18 4 100 10010 010011 1101 010011 0010 D18 5 101 10010 010011 1010 010011 1010 D19 4 100 10011 110010 1101 110010 0010 D19 5 101 10011 110010 1010 110010 1010 D20 4 100 10100 001011 1101 001011 0010 D20 5...

Page 123: ...0111 0001 101000 1110 D16 6 110 10000 011011 0110 100100 0110 D16 7 111 10000 011011 0001 100100 1110 D17 6 110 10001 100011 0110 100011 0110 D17 7 111 10001 100011 0111 100011 0001 D18 6 110 10010 010011 0110 010011 0110 D18 7 111 10010 010011 0111 010011 0001 D19 6 110 10011 110010 0110 110010 0110 D19 7 111 10011 110010 1110 110010 0001 D20 6 110 10100 001011 0110 001011 0110 D20 7 111 10100 00...

Page 124: ...j CurrentRD abcdie fghj K28 0 000 11100 001111 0100 110000 1011 K28 6 110 11100 001111 0110 110000 1001 K28 1 001 11100 001111 1001 110000 0110 K28 7 111 11100 001111 1000 110000 0111 K28 2 010 11100 001111 0101 110000 1010 K23 7 111 10111 111010 1000 000101 0111 K28 3 011 11100 001111 0011 110000 1100 K27 7 111 11011 110110 1000 001001 0111 K28 4 100 11100 001111 0010 110000 1101 K29 7 111 11101 ...

Page 125: ...vision History This appendix provides a list of the major differences between revisions of the MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MC92603RM This is the initial version of the manual so there currently are no changes to the document ...

Page 126: ...C 2 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA ...

Page 127: ...nment Refers to the transition tracking loop recovering data bits from the serial input stream Byte Eight bits of uncoded data Byte alignment Receiver identification of character boundaries through use of Idle character recognition C Character An 8B 10B encoded byte of data D Double data rate DDR The data is transferred on both the rising and falling edge of the clock rather than on just the risin...

Page 128: ...s responsible for transferring data to and from the physical layer N Negated Indicates inactive state of signal has been set Refers to either inputs or outputs P Physical coding sublayer PCS PCS is defined as part of a sublayer in the IEEE Std 802 3 2002 4 The PCS sublayer encodes data bits into code groups that can be transmitted over the physical medium It is used to coup the Media Independent I...

Page 129: ...er a link Equal to the difference between the number of one and zero symbols transmitted S SerDes Serializer deserializer Symbol One piece of information sent across the link different from a bit in that bit implies data where symbol is encoded data T Ten bit interface physical layer TBI PHY interface W Word synchronization Alignment of two or more receivers data by adjusting for differences in me...

Page 130: ...Glossary 4 MC92603 Quad Gigabit Ethernet Transceiver Reference Manual MOTOROLA ...

Page 131: ...arity calculating B 3 E Electrical characteristics 7 1 specifications 7 1 F Features 1 2 G General parameters 7 1 H Half speed mode 3 7 I IEEE Std 1149 1 implementation 6 1 Input amplifier 3 5 Instruction register 6 2 Instructions 6 2 J JTAG I O timing diagram 7 14 I O timing specification 7 14 L Link differential input timing specification 7 12 output specification 7 12 M MC92604 block diagram 1 ...

Page 132: ...3 2 functional description 3 5 interface signals 3 3 Reference clock specification 7 11 References 1 7 Repeater mode 2 6 3 7 Revision history 1 7 S Startup 5 2 T TAP interface signals 6 1 Test access port interface signals 6 1 Transition density B 1 Transition tracking loop 3 6 Transition tracking loop and data recovery 3 6 Transmission characters naming types B 2 overview B 1 Transmitter 2 1 DDR ...

Page 133: ...rface MDIO Index System Design Considerations Test Features 1 2 3 4 5 6 Glossary of Terms and Abbreviations 8B 10B Coding Scheme Ordering Information Package Description Electrical Specifications and Characteristics Revision History 7 8 A B C GLO IND ...

Page 134: ...rface MDIO Index System Design Considerations Test Features 1 2 3 4 5 6 Glossary of Terms and Abbreviations 8B 10B Coding Scheme Ordering Information Package Description Electrical Specifications and Characteristics Revision History 7 8 A B C GLO IND ...

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